L6717TR STMicroelectronics, L6717TR Datasheet

Page 1

Features ■ Hybrid controller for both PVI and SVI CPUs ■ Dual controller with 2 embedded high current drivers + 2 PWM for external driver for CPU CORE and 1 embedded high current driver for CPU NB ■ Dynamic phase ...

Page 2

Contents Contents 1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4 1.1 Application circuit . . . . . . . ...

Page 3

L6717 7 Output voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

Typical application circuit and block diagram 1 Typical application circuit and block diagram 1.1 Application circuit Figure 1. Typical 4+1 application circuit PWRGOOD 35 PWROK 1 VID0 / VFIX 34 VID1 / ...

Page 5

L6717 Figure 2. Typical 3+1 application circuit PWRGOOD 35 PWROK 1 VID0 / VFIX 34 VID1 / CORE_TYPE 33 PVI / SVID Bus VID2 / SVD 32 VID3 / SVC 31 VID4 / ...

Page 6

Typical application circuit and block diagram Figure 3. Typical 2+1 application circuit PWRGOOD 35 PWROK 1 VID0 / VFIX 34 VID1 / CORE_TYPE 33 PVI / SVID Bus VID2 / SVD 32 VID3 ...

Page 7

L6717 1.2 Block diagram Figure 4. Block diagram VCCDR EMBEDDED DRIVER GND_PAD CORE PHASE #2 LTB COMP FB FBG VSEN 64k 64k Typical application circuit and block diagram EMBEDDED DRIVER CORE PHASE #1 PWM2 DUAL CHANNEL OSCILLATOR (4+1) I DROOP ...

Page 8

Pins description and connection diagrams 2 Pins description and connection diagrams Figure 5. Pins connection (Top view) 2.1 Pin descriptions Table 2. Pin description Pin# Name System-wide Power Good input (Ignored in PVI mode). Internally pulled-low by 10μA. When low, ...

Page 9

L6717 Table 2. Pin description (continued) Pin# Name CORE error amplifier inverting input Connect with a resistor R voltage positioning is sourced from this pin. CORE output voltage monitor. 6 VSEN It manages OVP and UVP protections and ...

Page 10

Pins description and connection diagrams Table 2. Pin description (continued) Pin# Name Channel 1 current sense positive input. 15 CS1P Connect through an R-C filter to the phase-side of the channel 1 inductor. See Section 11 Channel 1 current sense ...

Page 11

L6717 Table 2. Pin description (continued) Pin# Name SDA - power manager When power manager See OVP - over voltage setting. 25 SDA / OVP When power manager the OVP protection for CORE and NB sections. Define the OVP threshold ...

Page 12

Pins description and connection diagrams Table 2. Pin description (continued) Pin# Name VCORE and NB Power Good open-drain output set free after SS as long as both the voltage planes are 35 PWRGOOD within specifications. Pull-up to ...

Page 13

L6717 2.2 Thermal data Table 3. Thermal data Symbol Thermal resistance junction to ambient R THJA (Device soldered on 2s2p PC board) R Thermal resistance junction to case THJC T Maximum junction temperature MAX T Storage temperature range STG T ...

Page 14

Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol GND CC, CCDRV to GND V , BOOTx V to PHASEx UGATEx to GND V PHASEx to GND, t < 200nsec. to ...

Page 15

L6717 3.2 Electrical characteristics V =12 V±15 Table 5. Electrical characteristics Symbol Parameter Supply current and power-on I VCC supply current CC I VCCDR supply current CCDR I BOOTx supply current BOOTx VCC turn-ON UVLO VCC VCC turn-OFF ...

Page 16

Electrical specifications Table 5. Electrical characteristics (continued) Symbol Parameter Voltage positioning (CORE and NB section) CORE Output voltage accuracy NB OFFSET bias voltage OFFSET current range OS OFFSET - I accuracy FB DROOP DROOP accuracy gain 0 ...

Page 17

L6717 Table 5. Electrical characteristics (continued) Symbol Parameter V OC_TOT CORE OC kI ILIM 1. Parameter(s) guaranteed by designed, not fully tested in production Test conditions I = 0μA LIM I = 100μA LIM Doc ID 17326 Rev 1 Electrical ...

Page 18

Device description and operation 4 Device description and operation L6717 is a hybrid CPU power supply controller compatible with both parallel (PVI) and serial (SVI) protocols for AMD Processors. The device provides complete control logic and protections for a high-performance ...

Page 19

L6717 5 Hybrid CPU support and CPU_TYPE detection L6717 is able to detect the type of the CPU-core connected and to configure itself accordingly. At system Start-up, on the rising-edge of the EN signal, the device monitors the status of ...

Page 20

Hybrid CPU support and CPU_TYPE detection Table 6. Voltage Identifications (VID) codes for PVI mode VID5 VID4 VID3 VID2 VID1 ...

Page 21

L6717 5.3 SVI - serial interface SVI is a two wire, clock and data, bus that connects a single master (CPU) to one slave (L6717). The master initiates and terminates SVI transactions and drives the clock, SVC, and the data, ...

Page 22

Hybrid CPU support and CPU_TYPE detection transition for the addressed section(s) or, more in general, react to the sent command accordingly. Refer to L6717 is able to manage individual power OFF for both the sections. The CPU may issue a ...

Page 23

L6717 Table 9. Data phase - serial VID codes Output SVI [6:0] voltage 000_0000 1.5500 000_0001 1.5375 000_0010 1.5250 000_0011 1.5125 000_0100 1.5000 000_0101 1.4875 000_0110 1.4750 000_0111 1.4625 000_1000 1.4500 000_1001 1.4375 000_1010 1.4250 000_1011 1.4125 000_1100 1.4000 000_1101 ...

Page 24

Hybrid CPU support and CPU_TYPE detection 5.4.2 PWROK de-assertion Anytime PWROK de-asserts, while EN is asserted, the controller uses the previously stored Pre-PWROK Metal VID and sets both CORE and NB planes voltage to the corresponding level performing an on-the-fly ...

Page 25

L6717 5.4.4 HiZ management L6717 is able to manage HiZ both for internal driver and for external drivers through the PWMx signals. When the controller needs to set HiZ state for a phase or section, it sets the corresponding PWMx ...

Page 26

Power manager I2C 6 Power manager I L6717 features a secondary power manager I management features as well as over-speeding for “enthusiastic” users. The power 2 manager I C bus is operative after the PWRGOOD signal is driven high at ...

Page 27

L6717 Refer to Figure 8, Figure 8. Power manager I Table 11. Power manager I bits Address phase 1:6 Always 110011b. Slave address. 7 According to ADDR connection, the device will act if addressed 1b. Default address ...

Page 28

Power manager I2C Table 12. Power manager I Command Data stream code [4:6] [1:2] xx 1CN [3] SIGN [4:8] OVRSPD [1:4] xxxx 000 [5:6] OV_NB [7:8] OV_CORE [1:5] xxxxx 001 [6:8] FSW 28/ command phase and data stream ...

Page 29

L6717 Table 12. Power manager I Command Data stream code [4:6] [1:4] xxxx 010 [5:6] k [7:8] k [1:3] xxx [4:5] DPMTH 011 [6] PSI_A [7] PSI_EN [8] DPM_ON 6.1.1 Overspeeding command (OVRSPD) This command allows to add a variable ...

Page 30

Power manager I2C See Table 12 and stream. Table 13. OVRSPD command - offset codification Data Offset to stream reference [4:8] [V] 00000 0.00 00001 0.05 00010 0.10 00011 0.15 00100 0.20 00101 0.25 00110 0.30 00111 0.35 1. Offset ...

Page 31

L6717 Table 15. FSW_ADJ command - switching frequency adjustment codification Data stream [6:8] 000 001 010 011 6.1.4 Droop function adjustment (DRP_ADJ) This command allows to adjust the slope for the output voltage load line once the external components are ...

Page 32

Power manager I2C Table 17. Power management flags Data stream bit [1:3] [4:5] [6] [7] [8] 6.2 Dynamic phase management (DPM) Dynamic phase management allows to adjust the number of working phases according to the delivered current still maintaining the ...

Page 33

L6717 When the soft start is over and once PWRGOOD rise to Logic “1”, L6717 can receive commands on power manager I Once DPM is enabled, L6717 starts monitoring the ILIM voltage: the voltage is compared with the internal V ...

Page 34

Output voltage positioning 7 Output voltage positioning Output voltage positioning is performed by selecting the controller operative-mode (SVI, PVI and V_FIX) and by programming the droop function and offset to the reference of both the sections (See Figure monitoring the ...

Page 35

L6717 7.1 CORE section - phase # programming CORE section implements a flexible interleaved-phase converter. To program the desired number of phase, simply short to GND the PWMx signal that is not required to be used according ...

Page 36

Output voltage positioning Figure 10. Current reading The current read through the CSxP / CSxN pairs is converted into a current I tional to the current delivered by each phase and the information about the average current = ΣI I ...

Page 37

L6717 7.4 CORE section - analog offset (Optional - I2CDIS = 3.3 V) When power manager I positive/negative offset to the CORE section. In this particular conditions, the pin SCL/OS becomes a virtual ground and allows programming a positive/negative offset ...

Page 38

Output voltage positioning command (k DRPNB (Figure 9). The output characteristic vs. load current is then given by VID R OUT_NB VID R Where R is the resulting Load-Line resistance implemented by the NB Section. LL_NB k value ...

Page 39

L6717 until the new code has reached. The output voltage rate of change will μsec. = 3.125 mV/μsec. Figure 11. PVI mode - on-the-fly VID transitions OTFVID Clock VID [0:5] Int. Reference T OTFVID ...

Page 40

Output voltage positioning 7.8 Soft-start L6717 implements a soft-start to smoothly charge the output filter avoiding high in-rush cur- rents to be required to the input power supply. In SVI mode, soft-start time is intended as the time required by ...

Page 41

L6717 8 Output voltage monitoring and protections L6717 monitors the regulated voltage of both sections through pin VSEN and NB_VSEN in order to manage OV, UV and PWRGOOD. The device shows different thresholds when in different operative conditions but the ...

Page 42

Output voltage monitoring and protections Figure 13. Analog OVP threshold When the voltage sensed by VSEN and/or NB_VSEN overcomes the OV threshold, the con- troller: – Permanently sets the PWM of the involved section to zero keeping ENDRV of that ...

Page 43

L6717 soon as the difference between the output and the input of this OpAmp is higher than 500mV, the device latches in HiZ. FLT pin is driven high. To recover from a latch condition, cycle VCC or EN. Figure 14. ...

Page 44

Output voltage monitoring and protections scale can be implemented. When the voltage present at the ILIM pin crosses V OC_TOT of all the sections OFF (HiZ). Typical design considers the intervention of the total current OC before the per-phase OC, ...

Page 45

L6717 8.4.2 NB section NB section performs per-phase over current: its maximum information current (I internally limited to I exceeds the end-of-scale current (i. low-side MOSFET, also skipping clock cycles, until the threshold is re-crossed (i.e. until I ...

Page 46

Main oscillator 9 Main oscillator The controller embeds a dual-oscillator: one section is used for the CORE and multi- phase programmable oscillator managing equal phase-shift among all phases and the other section is used for the NB ...

Page 47

L6717 10 High current embedded drivers L6717 provides high-current driving control for CORE and NB sections. The driver for the high-side MOSFET use BOOTx pin for supply and PHASEx pin for return. The driver for the low-side MOSFET use the ...

Page 48

High current embedded drivers 10.2 Power dissipation It is important to consider the power that the device is going to dissipate in driving the exter- nal MOSFETs in order to avoid overcoming the maximum junction operative temperature. Two main terms ...

Page 49

L6717 11 System control loop compensation The device embeds two separate and independent control loops for CORE and NB section. The control loop for NB section is a simple voltage-mode control loop with (optional) voltage positioning featured when DROOP pin ...

Page 50

System control loop compensation Figure 18. Control loop bode diagram and fine tuning (not in scale LOOP K R [dB] F ω ω ω To obtain the desired shape an R implementation. A zero at ...

Page 51

L6717 12 LTB Technology ® LTB Technology by reducing the system latencies and immediately turning ON all the phases to provide the correct amount of energy to the load. By properly designing the LTB network as well as the LTB ...

Page 52

Layout guidelines 13 Layout guidelines Layout is one of the most important things to consider when designing high current applications. A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radiation and a ...

Page 53

L6717 For heat dissipation, place copper area under the IC. This copper area must be connected with internal copper layers through several VIAs to improve the thermal conductivity. The combination of copper pad, copper plane and VIAs under the controller ...

Page 54

VFQFPN48 mechanical data and package dimensions 14 VFQFPN48 mechanical data and package dimensions In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade ...

Page 55

L6717 15 Revision history Table 21. Document revision history Date 29-Mar-2010 Revision 1 Initial release. Doc ID 17326 Rev 1 Revision history Changes 55/56 ...

Page 56

... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...