MAX8688ALETG+ Maxim Integrated Products, MAX8688ALETG+ Datasheet - Page 31

• Manufacturer Part Number: MAX8688ALETG+
• Description: IC PWR SUPPLY CTRLR/MONTR 24TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8688ALETG+

• Applications: Power Supply Controller/Monitor
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 6.7mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TQFN Exposed Pad
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The PMBUS_REVISION command returns the revision
of the PMBus specification to which the MAX8688 is
compliant.
The command has 1 data byte. Bits [7:5] indicate the
revision of PMBus specification Part I to which the
MAX8688 is compliant. Bits [4:0] indicate the revision of
PMBus specification Part II to which the MAX8688 is
compliant. The permissible values are shown in Table 7.
This command is read only.
The default PMBUS_REVISION value is 00h which indi-
cates that the MAX8688 is compliant with Part I Rev 1.0
and Part II Rev 1.0.
The MFR_ID command returns the MAX8688 manufac-
turer’s identification.
The default MFR_ID value is 4D01h.
This command is read only.
Table 7. PMBus Revision Data Byte
Contents
Table 8. MFR_MODE Bit Definition
BITS [7:5]
15:8
BIT
7
6
000
A3 Control Enable
Clock Out Enable
Input Clock Time
BIT NAME
Factor
REVISION
PART I
1.0
______________________________________________________________________________________
Digital Power-Supply Controller/Monitor
PMBUS_REVISION (98h)
This is equivalent to the number of external clock cycles provided to CLKIO in 100µs - 2.
MFR_MODE[15:8] = f
example, when f
external input clock range is from 100kHz (MFR_MODE[15:8] = 8) to 2.5MHz (MFR_MODE[15:8] =
248).
These bits are ignored if the internal clock source is selected as the time base (Clock Source
Select bit = 0)
The Clock Out Enable bit allows the output of a 1MHz reference clock to CLKIO for synchronizing
multiple MAX8688s. Setting this bit to 1 enables the 1MHz output on CLKIO. When this bit is cleared
to 0, no reference clock is outputted.
Setting this bit to 1 enables A3/ONOFF to function as a POL ON/OFF input control. Clearing this bit to
0 ignores the A3/ONOFF state and the MAX8688 is controlled by the OPERATION command alone.
See the A3/ONOFF Operation section.
BITS [4:0]
00000
MFR_ID (99h)
EXT_CLK
REVISION
PART II
EXT_CLK
1.0
= 1MHz, f
/10kHz - 2 where f
EXT_CLK
The MFR_MODEL command returns the MAX8688
model number.
The default MFR_MODEL value is 4101h.
This command is read only.
The MFR_REVISION command reads the ASCII charac-
ters that contain the MAX8688 revision number with a
block read command.
The default MFR_REVISION value is 3201h.
This command is read only.
The MFR_SMB_LOOPBACK command returns the data
word previously received by the MAX8688. The SMBus
master writes a data word to the MAX8688 using this
command and then retrieves the data word. A valid
communication channel is established if the master
reads back the same word.
Note that if another command is sent in between the write
MFR_SMB_LOOPBACK command and the read
MFR_SMB_LOOPBACK command, the MAX8688 returns
whatever last command data word it receives.
The MFR_MODE command is used to configure the
MAX8688 to support manufacturer specific commands.
The MFR_MODE command is described in Table 8.
The default MFR_MODE value is 00h.
with PMBus Interface
/10kHz = 100, MFR_MODE[15:8] = 100 – 2 = 98. Valid
DESCRIPTION
EXT_CLK
is the frequency of the external clock. For
MFR_SMB_LOOPBACK (D0h)
MFR_REVISION (9Bh)
MFR_MODEL (9Ah)
MFR_MODE (D1h)
31