MAX16066ETL+ Maxim Integrated Products, MAX16066ETL+ Datasheet - Page 44

• Manufacturer Part Number: MAX16066ETL+
• Description: IC SYSTEM MANAGER 8CH 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX16066ETL+

• Applications: Power Supply Monitor, Sequencer
• Voltage - Supply: 2.8 V ~ 14 V
• Current - Supply: 4.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Number Of Voltages Monitored: 8
• Undervoltage Threshold: 2.7 V
• Manual Reset: Resettable
• Watchdog: Yes
• Battery Backup Switching: No
• Power-up Reset Delay (typ): 200 us
• Supply Voltage (max): 14 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 10 mA
• Maximum Power Dissipation: 2105 mW
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Chip Enable Signals: No
• Internal Hysteresis: Yes
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
The block write procedure is the following:
1)
2)
3)
4)
5)
6)
7)
8)
9)
10) Repeat steps 8 and 9 n - 1 times.
11) The master sends a STOP condition.
When PEC is enabled, the Block Write protocol becomes:
1)
2)
3)
4)
5)
6)
7)
8)
9)
10) Repeat 8 and 9 n - 1 times.
11) The master sends an 8-bit PEC byte.
12) The slave asserts an ACK on the data line (if PEC is
13) The master generates a STOP condition.
The block read protocol (see Figure 14) allows the
master device to read a block of up to 16 bytes from
memory. Read fewer than 16 bytes of data by issuing
an early STOP condition from the master, or by generat-
ing a NACK with the master. The destination address
should be preloaded by a previous send byte command;
otherwise the block read command begins to read at
the current address pointer. If the number of bytes to
be read causes the address pointer to exceed 8Fh for
44
The master sends a START condition.
The master sends the 7-bit slave address and a
write bit (low).
The addressed slave asserts an ACK on SDA.
The master sends the 8-bit command code for a
block write (A5h).
The addressed slave asserts an ACK on SDA.
The master sends the 8-bit byte count (1 byte to 16
bytes), n.
The addressed slave asserts an ACK on SDA.
The master sends 8 bits of data.
The addressed slave asserts an ACK on SDA.
The master sends a START condition.
The master sends the 7-bit slave ID plus a write
bit (low).
The addressed slave asserts an ACK on the data line.
The master sends 8 bits of the block write command code.
The slave asserts an ACK on the data line.
The master sends an 8-bit byte count (min 1, max
16), n.
The slave asserts an ACK on the data line.
The master sends 8 bits of data.
The slave asserts an ACK on the data line.
good, otherwise NACK).
_____________________________________________________________________________________
Block Read
the configuration register or configuration flash or FFh
in user flash, the address pointer stays at 8Fh or FFh,
respectively. The block read procedure is the following:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a write
3) The addressed slave asserts an ACK on SDA.
4) The master sends 8 bits of the block read command (A6h).
5) The slave asserts an ACK on SDA, unless busy.
6) The master generates a REPEATED START condition.
7) The master sends the 7-bit slave address and a read
8) The slave asserts an ACK on SDA.
9) The slave sends the 8-bit byte count (16).
10) The master asserts an ACK on SDA.
11) The slave sends 8 bits of data.
12) The master asserts an ACK on SDA.
13) Repeat steps 11 and 12 up to fifteen times.
14) The master asserts a NACK on SDA.
15) The master sends a STOP condition.
When PEC is enabled, the Block Read protocol becomes:
1)
2)
3)
4)
5)
6)
7)
8)
9)
10) The master asserts an ACK on the data line.
11) The slave sends 8 bits of data.
12) The master asserts an ACK on the data line.
13) Repeat 11 and 12 up to 15 times.
14) The slave sends an 8-bit PEC byte.
15) The master asserts a NACK on the data line.
16) The master generates a STOP condition.
bit (low).
bit (high).
The master sends a START condition.
The master sends the 7-bit slave ID plus a write
bit (low).
The addressed slave asserts an ACK on the data line.
The master sends 8 bits of the block read command
code.
The slave asserts an ACK on the data line unless
busy.
The master sends a REPEATED START condition.
The master sends the 7-bit slave ID plus a read
bit (high).
The slave asserts an ACK on the data line.
The slave sends an 8-bit byte count (16).