ISL8724IRZ Intersil, ISL8724IRZ Datasheet - Page 8

• Manufacturer Part Number: ISL8724IRZ
• Description: IC POWER SUPPLY SEQUENCER 24QFN
• Manufacturer: Intersil

Specifications of ISL8724IRZ

• Applications: Power Supply Sequencer
• Voltage - Supply: 2.5 V ~ 5 V
• Current - Supply: 270µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

Typical Performance Curves
Using the ISL8723EVAL1 Platform
The ISL8723EVAL1 platform allows evaluation of the
ISL8723, easily providing access to the critical nodes (see
Figure 22 for schematic and Figure 23 for a photograph of
the evaluation platform).
The board has a SMD layout with a ISL8723 illustrating the
possible small implementation size for a typical four rail
sequencing application. There are bias and function labeled
test points to give access to the IC pins for evaluation.
Remember that significant current or capacitive loading of
particular I/O pins will affect functionality and performance.
The default configuration of the ISL8723EVAL1 circuit was
built around the following design assumptions:
1. Using the ISL8723IR
2. The four supplies being sequenced are 5V (IN_A), 3.3V
3. The desired order turn-on sequence is 5V first, then 3.3V
4. The desired turn-off sequence is first the 2.5V, the 3.3V
FIGURE 11. GATE TURN-OFF/ON (DIS)CHARGE CURRENT
(IN_B), 2.5V (IN_D) and 1.5V (IN_C), the UVLO levels
are ~80% of nominal voltages. Resistors chosen such
that the total resistance of each divider is ~ 10k using
standard value resistors to approximate 80% of
nominal voltage supply = 0.63V on UVLO input.
about 12ms later then the 2.5V supply about 19ms later
and lastly the 1.5V supply about 40ms later.
12ms later, then the 1.5V supply about 36ms later and
lastly the 5V supply about 72ms after that.
10.3
10.2
10.1
10.0
1.29
1.28
1.27
1.26
1.25
1.24
1.23
9.9
9.8
9.7
9.6
9.5
9.4
-40
-40
DLY_OFF Vth
FIGURE 9. BIAS POWER ON RESET
DLY_ON Vth
-20
-20
0
0
TEMPERATURE (°C)
TEMPERATURE (°C)
25
25
8
45
45
I_GATE_OFF
75
75
I_GATE_ON
(Continued)
85
85
100
100
ISL8723, ISL8724
125
125
All scope shots are taken from ISL8723EVAL1 board.
Figures 13 and 14 illustrate the desired turn-on and turn-off
sequences respectively. The sequencing order and delay
between voltages sequencing is set by external capacitance
values so other than that illustrated can be accomplished.
Figures 15 and 16 illustrate the timing relationships between
the EN input, RESET, DLY and GATE outputs and the VOUT
voltage for a single channel being turned on and off
respectively.
RESET and SYSRST functionality and relationships are
shown in Figures 17 through 21.
Figure 17 illustrates that with a rising VDD, EN tied to VDD,
and all UVLO configured to be satisfied, both the RESET and
SYSRST are held low before V
to go high once the last UVLO is satisfied and RESET is
released to go high at t
Figure 18 shows GATE and RESET response to SYSRST
being pulled low.
Figure 19 shows EN high to SYSRST delay with all UVLO
inputs satisfied.
Figure 20 shows RESET and SYSRST delay to EN pulled low.
Figure 21 shows ~8µs of glitch filter duration, t
which the RESET and SYSRST do not react.
5. LED off indicates sequence has completed and RESET
has released and pulled high.
FIGURE 12. FAULT GATE TURN-OFF SINK CURRENT
6.0
5.8
5.6
5.4
5.2
5.0
4.8
100
90
80
70
60
50
40
-40
-40
FIGURE 10. CHARGE PUMP VOLTAGE
-20
V DD = 5V
-20
0
0
RSTdel
TEMPERATURE (°C)
TEMPERATURE (°C)
25
25
after the last GATE is high.
DD
45
45
= 1V. SYSRST is released
V DD = 2.5V
75
75
85
85
FIL
during
100
100
April 22, 2009
FN6413.1
125
125