ISL6505CB Intersil, ISL6505CB Datasheet
ISL6505CB
Specifications of ISL6505CB
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ISL6505CB Summary of contents
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... SB • Pb-Free Plus Anneal Available (RoHS Compliant) voltage is applied SB Applications • ACPI-Compliant Power Regulation for Motherboards Ordering Information PART NUMBER ISL6505CB* ISL6505CR* ISL6505CRZ* (Note 1) ISL6505EVAL1 ISL6505EVAL2 Add “-T” suffix for tape and reel. NOTE: 1. Intersil Pb-free plus anneal products employ special Pb-free ...
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Block Diagram 3V3DLSB EA3 + DR1 - TO UV DETECTOR FB1 FAULT UV DETECTOR UV COMP 4.10V 5VDL GND 3V3DL 5V 3V3 EA4 - + 4.4V/3.4V 3V3 MONITOR 5V MONITOR 2.75V/2.60V 4.5V/4.25V MONITOR AND CONTROL + 10 µ A 0.80V ...
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Simplified Power System Diagram +5V IN +12V IN +5V SB +3.3V IN FAULT Q2 Q3 3.3V /3.3V DUAL SB 3. OUT1 R21 SHUTDOWN SX, EN5, LAN 4 Typical Application +5V IN +12V IN +5V SB +3. ...
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Absolute Maximum Ratings Supply Voltage +7.0V 5VSB DLA . ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued) PARAMETER 1.2V LINEAR REGULATOR (V ) VID OUT2 1V2VID Regulation 1V2VID Nominal Voltage Level 1V2VID Undervoltage Rising Threshold 1V2VID Undervoltage Hysteresis 1V2VID Output Current ...
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Pinouts ISL6505 (20 LEAD WIDE SOIC) TOP VIEW 1 FB1 DR1 2 3V3DLSB 3 3V3DL 4 1V2VID 5 3V3 EN5 Functional Pin Description (Pin numbers for SOIC and QFN) 3V3 (Pin 6 ...
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SS (Pin 17 SOIC; Pin 14 QFN) Connect this pin to a small ceramic capacitor (no less than 5nF; 0.1µF recommended). The internal soft-start (SS) current source along with the external capacitor creates a voltage ramp used to control the ...
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The internal circuitry does not allow the transition from an S4/S5 (suspend to disk/soft off) state (suspend to RAM) state; however, it does allow the transition from S3 to S4/S5. The only ‘legal’ transitions are from an ...
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Soft-Start into Sleep States (S3, S4/S5) The 5V POR function initiates the soft-start sequence internal 10µA current source charges an external capacitor. The error amplifiers’ reference inputs are clamped to a level proportional to the SS (soft-start) pin ...
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V DUAL SB OUT1 up right after bias voltage surpasses POR level (but if LAN = GND, then V output will not come up until the soft-start OUT1 ramp, along with V ; see Figure 9). ...
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Application Guidelines Soft-Start Interval The 5V output of a typical ATX supply is capable of SB 725mA, with newer models rated for 1.0A, and even 2.0A. During power- sleep state, the 5V needs to provide sufficient current to ...
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Since the pin can nominally sink 1.2mA with only a 0.1V drop, a 1kΩ resistor will match that condition. The minimum input low logic level is typically around 25-30% of the 1.2V supply (0.3V in this example), and the ...
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Layout Considerations The typical application employing an ISL6505 is a fairly straight forward implementation. Like with any other linear regulator, attention has to be paid to the few potentially sensitive small signal components, such as those connected to sensitive nodes ...
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The output voltage drop is heavily dependent on the ESR (equivalent series resistance) of the output capacitor bank, the choice of capacitors should be such as to maintain the output voltage above the lowest allowable regulation level. Input Capacitors Selection ...
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... Q4 can also be a PNP transistor, such as an MMBT2907AL. For additional, more detailed information on the circuit, including a Bill-of-Materials and circuit board description, see Application Note AN1053. Also see Intersil Corporation’s web page (www.intersil.com). Q6 3V3 5V ...
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... Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220VHHC Issue I except for the " ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...