BD3500FVM-TR Rohm Semiconductor, BD3500FVM-TR Datasheet - Page 10

• Manufacturer Part Number: BD3500FVM-TR
• Description: IC REG LDO 1.8V NCH FET 8MSOP
• Manufacturer: Rohm Semiconductor
• Type: Positive Fixedr

Specifications of BD3500FVM-TR

• Number Of Outputs: 1
• Voltage - Output: 1.8V
• Voltage - Input: 4.5 ~ 5.5 V
• Operating Temperature: -10°C ~ 100°C
• Package / Case: 8-MSOP
• Polarity: Positive
• Output Type: Fixed
• Output Voltage: 1.8 V
• Line Regulation: 0.5 % / V
• Load Regulation: 10 mV
• Input Voltage Max: 5.5 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Maximum Power Dissipation: 437.5 mW
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

●Application circuit
●Directions for pattern layout of PCB
BD3504FVM,BD3500FVM,BD3501FVM,BD3502FVM
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www.rohm.com
・Because a VIN input capacitor causes impedance to drop, mount it as close to the VIN terminal as possible and use thick
・Because the NRCS terminal is analog I/O, take care to noise. In particular, high-frequency noise of GND may cause IC
・The VFB terminal is an output voltage sense line. Effects of wiring impedance can be ignored by sensing the output
・Because the GND terminal is GND to be used in analog circuit inside BD3501/02/04FVM, connect it at one point to
・The G terminal is a terminal for gate drive. If long wiring is inevitable, increase the pattern width and lower impedance.
・Heat generated in the output transistor can be calculated by:
・Connect the output capacitor with thick short wiring so that the impedance is lowered. Connect capacitor GND to
wiring patterns. In the event that it causes the wire to come in contact with the inner-layer ground plane, use a plurality of
through holes.
maloperation through capacitors. It is recommended to connect GND of NRCS capacitor to IC GND terminal at one
point.
voltage from the load side, but increased sense wiring causes VFB to be susceptible to noise, to which care must be
taken.
inner-layer GND of substrate by as short pattern as possible. Arrange a bypass capacitor across VCC and GND as close
as possible so that a loop can be minimized.
(VIN - VOUT) × Io(Max)
Design heat generation not to exceed the guarantee temperature of transistor.
inner-layer GND plane by a plurality of through holes.
Ven
C3
C3
C2
Vcc
Vcc
C1
C1
1
2
3
4
1
2
3
4
10/16
8
7
6
5
8
7
6
5
Ven
R1’
R2
R1
R2’
C4
C4
C5
+
+
C2
Technical Note
2010.05 - Rev.A
VIN
VIN