ISL8500IRZ Intersil, ISL8500IRZ Datasheet - Page 13

• Manufacturer Part Number: ISL8500IRZ
• Description: IC PWM REG 2A BUCK 12-DFN
• Manufacturer: Intersil
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of ISL8500IRZ

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 0.6 ~ 19 V
• Current - Output: 2A
• Frequency - Switching: 500kHz
• Voltage - Input: 4.5 ~ 25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: 12-DFN
• Voltage - Supply: 4.5 V ~ 25 V
• Frequency-max: 550kHz
• Duty Cycle: 94%
• Pwm Type: Voltage Mode
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
Feedback Compensation
Figure 21 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
amplifier output (V
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V
PWM wave is smoothed by the output filter (L
The modulator transfer function is the small-signal transfer
function of V
Gain and the output filter (L
break frequency at F
the modulator is simply the input voltage (V
peak-to-peak oscillator voltage ΔV
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL8500) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180°. Equation 8 relates the compensation network’s poles,
F LC
FIGURE 21. VOLTAGE-MODE BUCK CONVERTER
OUT
ΔV
=
OSC
FB
) is regulated to the Reference voltage level. The error
------------------------------------------ -
2π x
. The goal of the compensation network is to provide
OSC
0dB
OUT
L O x C O
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
1
COMPARATOR
) and adequate phase margin. Phase margin
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
/V
V
ISL8500
E/A
E/A
PWM
E/A
LC
Z
+
-
) is compared with the oscillator (OSC)
FB
-
+
COMP
. This function is dominated by a DC
C
and a zero at F
REFERENCE
2
REFERENCE
C
O
+
-
1
IN
13
DRIVER
R
F ESR
and C
Z
2
at the PHASE node. The
IN
OSC
FB
=
D
O
Z
), with a double pole
FB
------------------------------------------- -
2π x ESR x C O
ESR
.
PHASE
R
(PARASITIC)
V
4
C
IN
3
Z
R
L
IN
. The DC Gain of
O
IN
1
1
) divided by the
R
ESR
O
3
C
V
and C
O
OUT
0dB
V
DDQ
(EQ. 7)
O
).
and
IN
ISL8500
zeros and gain to the components (R
C
poles and zeros of the compensation network:
Compensation Break Frequency Equations
Figure 22 shows an asymptotic plot of the DC/DC
converter’s gain vs frequency. The actual Modulator Gain
has a high gain peak due to the high Q factor of the output
filter and is not shown in Figure 22. Using the previously
mentioned guidelines should give a Compensation Gain
similar to the curve plotted. The open loop error amplifier
gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The Closed Loop Gain is constructed on the graph
of Figure 4 by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
F
F
FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
1. Pick Gain (R
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
FB
3
Z1
Z2
100
-20
-40
-60
) in Figure 22. Use the following guidelines for locating the
80
60
40
20
0
and Z
=
=
----------------------------------- -
2π x R
------------------------------------------------------ -
2π x R
10
(R
20LOG
MODULATOR
2
IN
/R
ST
ND
ST
ND
(
1
1
to provide a stable, high bandwidth (BW) overall
GAIN
)
2
100
1
Zero Below Filter’s Double Pole (~75% F
Pole at the ESR Zero.
Zero at Filter’s Double Pole.
Pole at Half the Switching Frequency.
x C
+
1
2
R
/R
2
3
1
) x C
) for desired converter bandwidth.
1k
F
Z1
P2
F
FREQUENCY (Hz)
3
LC
F
Z2
with the capabilities of the error
10k
F
F
F
P1
P2
F
P1
ESR
(V
=
=
IN
100k
20LOG
F
-------------------------------------------------------- -
2π x R
----------------------------------- -
2π x R
/ΔV
1
P2
, R
OSC
OPEN LOOP
ERROR AMP GAIN
2
1
1M
, R
)
2
3
x
x C
3
1
COMPENSATION
⎛
⎜
⎝
, C
CLOSED LOOP
December 10, 2007
C
--------------------- -
C
3
1
1
10M
1
GAIN
+
x C
GAIN
, C
C
2
2
(EQ. 8)
2
LC
FN6611.0
⎞
⎟
⎠
, and
).