ISL6534CRZ-T Intersil, ISL6534CRZ-T Datasheet - Page 18

• Manufacturer Part Number: ISL6534CRZ-T
• Description: IC CTRLR PWM DUAL LINEAR 32-QFN
• Manufacturer: Intersil

Specifications of ISL6534CRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1MHz
• Duty Cycle: 87.5%
• Voltage - Supply: 3.3 V ~ 12 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 1MHz
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL6534CRZ-TTR

Feedback Compensation Equations
This section highlights the design consideration for a voltage-
mode controller requiring external compensation. To address a
broad range of applications, a type-3 feedback network is
recommended (see Figure 15).
Figure 16 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable to the
ISL6534 circuit. The output voltage (V
reference voltage, VREF. The error amplifier output (COMP pin
voltage) is compared with the oscillator (OSC) modified saw-
tooth wave to provide a pulse-width modulated wave with an
amplitude of V
smoothed by the output filter (L and C). The output filter
capacitor bank’s equivalent series resistance is represented by
the series resistor E.
FIGURE 16. VOLTAGE-MODE BUCK CONVERTER
FIGURE 15. COMPENSATION CONFIGURATION FOR ISL6534
CIRCUIT
PWM
R1
COMP
COMPENSATION DESIGN
CIRCUIT
IN
R2
at the PHASE node. The PWM wave is
HALF-BRIDGE
OSCILLATOR
V
OSC
C2
E/A
DRIVE
R3
C3
C1
R2
ISL6534
C2
+
-
VREF
C1
18
COMP
FB
FB
UGATE
LGATE
PHASE
EXTERNAL CIRCUIT
OUT
V
R3
Ro
DIFF
V
) is regulated to the
IN
R1
ISL6534
(V
OUT
C3
L
)
V
D
OUT
C
E
ISL6534
The modulator transfer function is the small-signal transfer
function of V
gain, given by d
filter, with a double pole break frequency at F
F
channel inductance and its DCR, while C and E represents
the total output capacitance and its equivalent series
resistance.
The compensation network consists of the error amplifier
(internal to the ISL6534) and the external R1-R3, C1-C3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
margin (better than 45degrees). Phase margin is the difference
between the closed loop phase at F
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 15. Use the following guidelines for locating the
poles and zeros of the compensation network:
F
5. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate
6. Calculate C1 such that F
7. Calculate C2 such that F
8. Calculate R3 such that F
CE
LC
value for R2 for desired converter bandwidth (F
setting the output voltage via an offset resistor connected
to the FB pin, Ro in Figure 16, the design procedure can
be followed as presented.
at 0.1 to 0.75 of F
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost at F
such that F
times F
Change the numerical factor to reflect desired placement
of this pole. Placement of F
reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at
the COMP pin and minimizing resultant duty cycle jitter.
R2
. For the purpose of this analysis, L and D represent the
=
C1
C2
R3
---------------------------
2π
=
=
=
=
⋅
-------------------------------------------- -
d
----------------------------------------------- -
2π R2 0.5 F
---------------------------------------------------------
2π R2 C1 F
--------------------- -
F
----------- - 1
1
F
V
MAX
SW
SW
L C
LC
OUT
0
OSC
R1
⋅
⋅
; typically 0.1 to 0.3 of F
⋅
P2
). F
–
MAX
⋅
/V
V
⋅
⋅
⋅
is placed below F
1
R1 F
SW
COMP
IN
C1
V
⋅
LC
IN
⋅
⋅
⋅
F
represents the switching frequency.
LC
/V
0
(to adjust, change the 0.5 factor to
LC
CE
. This function is dominated by a DC
OSC
F
Z1
–
P1
Z2
CE
1
C3
is placed at a fraction of the F
, and shaped by the output
is placed at F
=
is placed at F
P2
----------------------- -
2π C E
=
0dB
SW
lower in frequency helps
CE
-------------------------------------------------
2π R3 0.7 F
⋅
SW
1
/F
(typically, 0.5 to 1.0
⋅
and 180
⋅
) and adequate phase
LC
, the lower the F
⋅
CE
LC
1
LC
LC
).
.
. Calculate C3
o
⋅
November 18, 2005
and a zero at
. The
SW
0
). If
FN9134.2
LC
Z1
,