ISL8105BCBZ-T Intersil, ISL8105BCBZ-T Datasheet - Page 7

• Manufacturer Part Number: ISL8105BCBZ-T
• Description: IC PWM CTRLR BUCK 1PHASE 8-SOIC
• Manufacturer: Intersil

Specifications of ISL8105BCBZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 330kHz
• Duty Cycle: 100%
• Voltage - Supply: 6.5 V ~ 14.4 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 330kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

soft-start ramp voltage exceeds the output; V
seamlessly ramping from there. If the output is pre-biased to
a voltage above the expected value, as in the red curve,
neither MOSFET will turn on until the end of the soft-start, at
which time it will pull the output voltage down to the final
value. Any resistive load connected to the output will help
pull down the voltage (at the RC rate of the R of the load and
the C of the output capacitance).
If the V
different supply that comes up after V
would go through its cycle, but with no output voltage ramp.
When V
V
100% duty cycle, with COMP/EN pin >4V). If V
there may be excessive inrush current charging the output
capacitors (only the beginning of the ramp, from zero to
V
changing the sequencing of the power supplies, or sharing
the same supply, or adding sequencing logic to the
COMP/EN pin to delay the soft-start until the V
ready (see “Input Voltage Considerations” on page 9).
If the IC is disabled after soft-start (by pulling COMP/EN pin
low), and then enabled (by releasing the COMP/EN pin),
then the full initialization (including OCP sample) will take
place. However, there is no new OCP sampling during
overcurrent retries. If the output is shorted to GND during
soft-start, the OCP will handle it, as described in the next
section.
IN
OUT
V
V
from zero up to the final expected voltage (at close to
V
OUT
OUT
OUT
matters here). If this is not acceptable, then consider
IN
t0
IN
OVER-CHARGED
NORMAL
PRE-BIASED
for the synchronous buck converter is from a
FIGURE 3. SOFT-START WITH PRE-BIAS
turns on, the output would follow the ramp of the
t1
7
BIAS
, the soft-start
OUT
t2
IN
IN
is too fast,
supply is
starts
ISL8105B
Overcurrent Protection (OCP)
The overcurrent function protects the converter from a
shorted output by using the bottom-side MOSFET's
ON-resistance, r
(R
Application Diagram). This method enhances the converter's
efficiency and reduces cost by eliminating a current sensing
resistor. If overcurrent is detected, the output immediately
shuts off, it cycles the soft-start function in a hiccup mode
(2 dummy soft-start time-outs, then up to one real one) to
provide fault protection. If the shorted condition is not
removed, this cycle will continue indefinitely.
Following POR (and 6.8ms delay), the ISL8105B initiates the
Overcurrent Protection sample and hold operation. The
BGATE driver is disabled to allow an internal 21.5µA current
source to develop a voltage across R
samples this voltage (which is referenced to the GND pin) at
the BGATE/BSOC pin, and holds it in a counter and DAC
combination. This sampled voltage is held internally as the
Overcurrent Set Point, for as long as power is applied, or
until a new sample is taken after coming out of a shut-down.
The actual monitoring of the bottom-side MOSFET's
on-resistance starts 200ns (nominal) after the edge of the
internal PWM logic signal (that creates the rising external
BGATE signal). This is done to allow the gate transition
noise and ringing on the LX pin to settle out before
monitoring. The monitoring ends when the internal PWM
edge (and thus BGATE) goes low. The OCP can be detected
anywhere within the above window.
If the regulator is running at high TGATE duty cycles (around
87% for 300kHz operation), then the BGATE pulse width
may not be wide enough for the OCP to properly sample the
r
there at all) for 3 consecutive pulses, then the third pulse will
be stretched and/or inserted to the 425ns minimum width.
This allows for OCP monitoring every third pulse under this
condition. This can introduce a small pulse-width error on the
output voltage, which will be corrected on the next pulse;
and the output ripple voltage will have an unusual 3-clock
pattern, which may look like jitter. If the OCP is disabled (by
choosing a too-high value of R
then the pulse stretching feature is also disabled. Figure 4
illustrates the BGATE pulse width stretching, as the width
gets smaller.
DS(ON)
BSOC
. For those cases, if the BGATE is too narrow (or not
) programs the overcurrent trip level (see Typical
DS(ON)
, to monitor the current. A resistor
BSOC
, or no resistor at all),
BSOC
. The ISL8105B
April 15, 2010
FN6447.2