NCP1380CDR2G ON Semiconductor, NCP1380CDR2G Datasheet
NCP1380CDR2G
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NCP1380CDR2G Summary of contents
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NCP1380 Quasi-Resonant Current-Mode Controller for High-Power Universal Off-Line Supplies The NCP1380 hosts a high−performance circuitry aimed to powering quasi−resonant converters. Capitalizing on a proprietary valley−lockout system, the controller shifts gears and reduces the switching frequency as the power loading becomes ...
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TYPICAL APPLICATION EXAMPLE HV−Bulk NCP1380 A/B ZCD / OPP OVP / OTP Figure 1. Typical Application Schematic for A and B Versions HV−Bulk NCP1380 C/D ZCD / OPP ...
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PIN FUNCTION DESCRIPTION Pin N5 Pin Name 1 ZCD Zero Crossing Detection Adjust the over power protection GND 5 DRV 6 V Supplies the controller CC 7 Fault Over voltage and Over temperature protection (A ...
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INTERNAL CIRCUIT ARCHITECTURE VDD Rpullup FB VDD ICt tpoi nt − Ct Discharge ZCD + − Vth ESD DRV 3 ms blanking end / 4 The 40 ms Time Out ...
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VDD R pul VDD ICt Ct + − tpoint Ct discharge ZCD + − Vth ESD DRV 3 ms blanking end / 4 The 40 ms Time Out is active ...
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MAXIMUM RATINGS TABLE Symbol V Maximum Power Supply voltage, V CC(MAX) I Maximum current for V CC(MAX Maximum driver pin voltage, DRV pin, continuous voltage DRV(MAX) I Maximum current for DRV pin DRV(MAX) V Maximum voltage on low ...
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ELECTRICAL CHARACTERISTICS 1 680 pF) For min/max values T CS fault T Symbol CURRENT COMPARATOR − CURRENT SENSE t Propagation Delay ILIM I Percentage of maximum peak current level at peak(VCO) ...
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ELECTRICAL CHARACTERISTICS 1 680 pF) For min/max values T CS fault T Symbol FEEDBACK SECTION R Internal pullup resistor FB(pullup) I Pin FB to current setpoint division ratio ratio V FB ...
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T , JUNCTION TEMPERATURE (°C) J Figure 5. V vs. Junction Temperature CC(on) 1.90 1.80 1.70 1.60 1.50 1.40 1.30 −40 − ...
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T , JUNCTION TEMPERATURE (°C) J Figure 11. V vs. Junction Temperature ILIM 1.265 1.245 1.225 1.205 1.185 1.165 1.145 1.125 −40 − ...
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T , JUNCTION TEMPERATURE (°C) J Figure 17. V vs. Junction Temperature ZCD(th) 3.50 3.40 3.30 3.20 3.10 3.0 2.90 −40 − ...
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T , JUNCTION TEMPERATURE (°C) J Figure 23. I vs. Junction Temperature OTP 10.4 10.2 10.0 9.8 9.6 9.4 9.2 −40 810 805 800 795 790 785 ...
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The NCP1380 implements a standard current−mode architecture operating in quasi−resonant mode. Due to a proprietary circuitry, the controller valley−jumping instability and steadily locks out in selected valley as the power demand goes down. Once the fourth valley is reached, the ...
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Figure 26. Operating Valley According to FB Voltage The valley detection is done by monitoring the voltage of the auxiliary winding of the transformer. A valley is detected when the voltage on pin 1 crosses down the 55 mV internal ...
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As the output load decreases (FB voltage decreases), the valleys are incremented from the first to the fourth. When the fourth valley is reached voltage further decreases below 0.8 V, the controller enters VCO mode. During VCO operation, ...
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Figure 29. Zoom Valley Transition nd rd Figure 30. Zoom Valley Transition http://onsemi.com 16 ...
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Figure 32. Zoom 4: 4 Time Out In case of extremely damped free oscillations, the ZCD comparator can be unable to detect the valleys. To avoid such situation, NCP1380 integrates a Time Out function that acts as a substitute clock ...
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− Vth leakage blanking 3 us pulse DRV Figure 33. Time Out Circuit Figure 34. Time Out Case n51: the 3 demag 5.5 us time out 40 ...
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Figure 35. Time Out Case n52: the 3 VCO operation occurs for FB voltage lower than 0.8 V (FB decreasing), or lower than 1.4 V (FB increasing). This corresponds to low output power. During VCO operation, the peak current is ...
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Figure 37 shows the implementation of the fault timer. CS LEB1 R sen se FB/4 ZCD/OPP OPP Soft−start Laux LEB2 V CS(stop) When the current in the MOSFET is higher than “Max Ip” ...
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Figure 38. Auto−Recovery Short−Circuit Protection on B and D Versions Figure 39. Latched Short−Circuit Protection on A and C Versions http://onsemi.com 21 ...
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The over power compensation is achieved by monitoring the signal on ZCD pin (pin 1). Indeed, a negative voltage applied on this pin directly affects the internal voltage reference setting the maximum peak current (Figure 40). When the power MOSFET ...
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OVERVOLTAGE / OVERTEMPERATURE DETECTION (A AND B VERSIONS) Overvoltage and overtemperature detection is achieved by reading the voltage on pin 7 (See Figure 41). VCC VDD Dz I OTP(REF) Fa ult NTC V Vclam p ...
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OVERVOLTAGE PROTECTION / BROWN−OUT (C AND D VERSIONS) The C and D versions of NCP1380 combine brown−out and overvoltage detection on pin 7. VCC HV−Bulk Dz VOVP Rbou OVP/BO 7 VDD IBO Rbol Vclamp Figure 43. ...
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... R and R . bou bol ORDERING INFORMATION Device NCP1380ADR2G NCP1380BDR2G NCP1380CDR2G NCP1380DDR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. R bol ) and the bulk R bou Package SOIC− ...
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... *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The products described herein (NCP1380), may be covered by one or more of the following U.S. patents; 6,362,067; pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein ...