NCP1380CDR2G ON Semiconductor, NCP1380CDR2G Datasheet - Page 22
NCP1380CDR2G
Manufacturer Part Number
NCP1380CDR2G
Description
IC PWM FLYBCK ISO CM 8SOIC
Manufacturer
ON Semiconductor
Datasheet
1.NCP1380ADR2G.pdf
(26 pages)
Specifications of NCP1380CDR2G
Pwm Type
Current Mode
Number Of Outputs
1
Frequency - Max
65kHz
Voltage - Supply
9.4 V ~ 28 V
Buck
No
Boost
No
Flyback
Yes
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
Yes
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (3.9mm Width)
Frequency-max
65kHz
Mounting Style
SMD/SMT
Operating Supply Voltage
- 0.3 V to + 28 V
Supply Current
+/- 30 mA
Maximum Operating Temperature
+ 125 C
Fall Time
25 ns
Minimum Operating Temperature
- 40 C
Rise Time
40 ns
Synchronous Pin
No
Topology
Quasi-Resonant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Duty Cycle
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NCP1380CDR2G
Manufacturer:
ON Semiconductor
Quantity:
2 000
the signal on ZCD pin (pin 1). Indeed, a negative voltage
applied on this pin directly affects the internal voltage
reference setting the maximum peak current (Figure 40).
winding voltage becomes a negative voltage proportional to
needed to bypass R
on−time, we obtain the following relationship:
Where:
N
/ N
V
V
using Equation 2. While selecting the value for R
must be careful not choosing a too low value for this resistor
in order to have enough voltage for zero−crossing detection
during the off−time. We recommend having at least 8 V on
ZCD pin, the maximum voltage being 10 V.
follows:
R
p,aux
in
OPP
ZCD
The over power compensation is achieved by monitoring
When the power MOSFET is turned−on, the auxiliary
To ensure optimal zero−crossing detection, a diode is
If we apply the resistor divider law on the pin 1 during the
By selecting a value for R
During the off−time, ZCD pin voltage can be expressed as
We can thus deduce the relationship between R
p
is the DC input voltage
:
is the negative OPP voltage
is the auxiliary to primary turn ration: N
R
V
ZCD
ZCD
R
R
R
) R
opl
ZCD
+
opl
opu
R
opu
Au x
+
ZCD
during the off−time.
V
+ *
R
aux
) R
opl
opl
* V
Rz cd
N
, we can easily deduce R
opl
V
p,aux
ZCD
Ropu
Ropl
d
V
* V
aux
V
V
Figure 40. Over Power Compensation Circuit
in
OPP
* V
ZCD
* V
OVER POWER COMPENSATION
ZCD/OPP
d
OPP
1
p,aux
DRV
opl
opl
(eq. 2)
= N
(eq. 3)
(eq. 4)
http://onsemi.com
ESD
protection
, we
and
opu
aux
Vt h
CS
22
the input voltage. As the auxiliary winding is already
connected to ZCD pin for the valley detection, by selecting
the right values for R
over power compensation.
Design example:
V
V
N
If we want at least 8 V on ZCD pin, we have:
We can choose: R
peak current by 37.5% at high line (370 Vdc). The
corresponding OPP voltage is:
Using Equation 2, we have:
Thus,
leakage blanking
aux
R
d
p,aux
For the over power compensation, we need to decrease the
R
= 0.6 V
ZCD
Tblank
opu
V IL IMIT
= 18 V
R
= 0.18
+
−
) R
+ 221
opt
V
OPP
opu
OPP
Ropl
R
+
R
+ *
ZCD
+ 0.375
opl
ZCD
−0.18
* R
+
+
N
opu
= 1 kW and R
p,aux
ZCD
V
18 * 0.6 * 8
aux
and R
( −0.3 )
370 * ( −0.3 )
V
+ 221
V
* V
lin
V
OPP
8
IpFlag
V
ILIM
* V
Demag
opl
ZCD
d
* V
+ −300 mV
, we can easily perform
OPP
opl
1k * 1k + 220 kW
[ 1.2
ZCD
= 1 kW.
+ 221
(eq. 5)
(eq. 6)
(eq. 7)
(eq. 8)