ISL6529ACR Intersil, ISL6529ACR Datasheet - Page 10

• Manufacturer Part Number: ISL6529ACR
• Description: IC CTRLR PWM DUAL REG 16-QFN
• Manufacturer: Intersil

Specifications of ISL6529ACR

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 650kHz
• Duty Cycle: 100%
• Voltage - Supply: 4.5 V ~ 13.2 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Frequency-max: 650kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

controllable closed loop transfer function of V
goal of component selection for the compensation network is
to provide a loop gain with high 0dB crossing frequency
(f
difference between the closed loop phase at f
degrees.
Compensation Break Frequency Equations
Follow this procedure for selecting compensation
components by locating the poles and zeros of the
compensation network:
Figure 7 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a high
gain peak dependent on the quality factor (Q) of the output
filter, which is not shown in Figure 7. Using the above
Poles:
Zeros:
1. Set the loop gain (R2/R1) to provide a converter
2. Place the first compensation zero, F
3. Position the second compensation zero, F
4. Locate the first compensation pole, F
5. Position the second compensation pole at half the
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin; repeat if necessary.
FIGURE 7. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
0dB
100
-20
-40
-60
80
60
40
20
bandwidth of one quarter of the switching frequency.
filter double pole (~75% F
output filter double pole, F
filter ESR zero, F
converter switching frequency, F
0
) and adequate phase margin. Phase margin is the
F
F
F
F
Z2
P1
P2
Z1
10
MODULATOR
20
=
=
=
=
log
GAIN
------------------------------------------------------ -
2π
------------------------------------------------------ -
2π
-----------------------------------
2π
-----------------------------------
2π


100
R2
-------- -
R1
×
F
×
×
×
Z1
(
R
R


R
R1
1
1
2
3
2
×
×
×
+
1
F
ESR
1
1K


C3
C1
LC
R3
C1
--------------------- -
C1
F
FREQUENCY (Hz)
Z2
)
.
+
×
×
F
C2
C2
ESR
10K
C3
10
LC
LC


F
P1
).
.
100K
SW
F
P2
.
Z1
P1
, below the output
1M
, at the output
ERROR AMP GAIN
OUT
COMPENSATION
0dB
Z2
OPEN LOOP
20
LOOP GAIN
, at the
log
/V
10M
and 180
GAIN
REF



(EQ. 10)
(EQ. 8)
(EQ. 9)
(EQ. 11)
----------------- -
V
V IN
OSC
. The



ISL6529A
procedure should yield a compensation gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
with the capabilities of the error amplifier.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Linear Regulator Feedback Compensation
The regulator may be compensated with a series 6.8kΩ
resistor and a 470pF capacitor connected between FB2 and
DRIVE2. This will provide compensation for all loads and
ranges of output capacitor values and a range of capacitor
ESR values from aluminum electrolytic to low-ESR organic
polymer capacitors. This will not insure optimum load
transient response since the regulator system, like an
internally compensated operational amplifier is
overcompensated.
To optimize transient response, when required, the regulator
should be in the actual application circuit with the desired
output capacitors and associated PC board parasitics and
load. The value of C4 would be reduced and the series
resistor, R12 adjusted for optimum rise and fall time, with a
minimum of overshoot.
Application Guidelines
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
600kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit board design minimizes the voltage
spikes in the converters.
As an example, consider the turn-off transition of the PWM
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower MOSFET and
parasitic diode. Any parasitic inductance in the switched
current path generates a large voltage spike during the
switching interval. Careful component selection, tight layout
of the critical components, and short, wide traces minimizes
the magnitude of voltage spikes.
There are two sets of critical components in a DC-DC converter
using the ISL6529A. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are the
small signal components which connect to sensitive nodes or
supply critical bypass current and signal coupling.
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
December 28, 2004
FN9127.1
P2