ISL6534CV-T Intersil, ISL6534CV-T Datasheet
ISL6534CV-T
Specifications of ISL6534CV-T
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ISL6534CV-T Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6534 ...
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... Ordering Information PART NUMBER PART MARKING ISL6534CV ISL6534CV ISL6534CVZ (See Note) ISL6534CVZ ISL6534CR ISL6534CR ISL6534CRZ (See Note) ISL6534CRZ ISL6534EVAL2 EVAL board NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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Block Diagram VCC5 30µA SS1/EN1 VCC5 30µA SS2/EN2 VCC5 30µA SS3/EN3 3.3V PGOOD COMP1 FB1 0.6V REFIN FB2 COMP2 GND 3 ISL6534 VCC VCC5 POWER 5.8V ON RESET AND CONTROL REFERENCE BIAS CURRENT 0.6V CLOCK AND SAWTOOTH GENERATOR PGOOD = ...
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Typical Application, DDRAM Controller VOLTAGE INPUTS REQUIRED VCC12 (12V) VCC (5V OR 5.8V FROM SHUNT) VIN1, VBS1 VIN2, VBS2 VIN3 VOUT1 VOUT2 VOUT1 (DDR) VTTREF VREF NOTE: Not all components are necessary in all applications. FIGURE 2. TYPICAL APPLICATION, DDRAM ...
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Typical Application, Independent Mode VOLTAGE INPUTS REQUIRED VCC12 (12V) VCC (5V OR 5.8V FROM SHUNT) VIN1, VBS1 VIN2, VBS2 VIN3 VOUT1 VOUT2 VREF (IND) VTTREF VREF NOTE: Not all components are necessary in all applications. 5 ISL6534 ISL6534 INDEPENDENT MODE ...
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Absolute Maximum Ratings Supply Voltage (VCC12 GND - 0.3V to 14.0V Supply Voltage (VCC, separate supply GND ...
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Electrical Specifications Operating Conditions: V PARAMETER ERROR AMPLIFIER (OUT1 and OUT2) Open-Loop Gain RL = 10kΩ to ground; (Note 7) Open-Loop Bandwidth CL = 100pF 10kΩ to ground; (Note 7) Slew Rate CL = 100pF 10kΩ ...
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Electrical Specifications Operating Conditions: V PARAMETER ENABLE/SOFT-START (SS/ Enable Threshold EN Rising EN falling Noise Immunity (noise de-glitch) (Note 7) Soft-Start Current I Soft-Start High Voltage End of ramp Output High Voltage To select DDR mode; (see ...
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Pin Description VCC This power pin supplies bias to the control functions. It can be connected to a nominal 5V (±5%) supply can function as a shunt regulator (nominal 5.8V), with an external pull-up resistor (nominally 150Ω to ...
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PGOOD This digital output is an open-drain pull-down device. When power is first applied to the IC, the output is pulled low, for power “Not Good”. After all 3 soft-start pins complete their ramp up with no faults (no short ...
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LG1 is shown with a pulse width shorter than LG2; this is just an arbitrary example, and it does not affect the rising edges 180 270 FIGURE 4. PHASE OF LG2 ...
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The advantage is that if either the VREF or desired output voltage changes going forward, the only board change needed is the value more resistors. The disadvantage is that since there ...
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OPEN-DRAIN LOGIC SIGNALS EN1, 2 EN3 C C SS1 SS2 FIGURE 8. 1 AND 2 ENABLED TOGETHER BUT HAVE INDEPENDENT SOFT-STARTS FULLY INDEPENDENT. The soft-start pins can share the same capacitor, to ramp them all at the same ...
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Once the power is “Good”, PGOOD will pull low if any of the 3 SS/EN pins is pulled low. Also short is detected on either switcher, then the PGOOD will pull low, for as long as the condition ...
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PERIOD (µs) FIGURE 12. TYPICAL CLOCK PERIOD vs FS_SYNC RESISTOR TO GND SYNC With multiple switching regulators running on the same board at similar, but independent frequencies, there ...
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The above formula determines how long the Soft-Start ramp time is. But since the outputs don’t turn on until the SS/EN pin reaches ~1V, that means the actual time the output ramps is only ~70% of the total SS ramp. ...
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... Choose the appropriate bandwidth and gain to meet the design goals. 4. Check with your local Intersil Field Applications for help in choosing compensation values for these special cases; improved tools are available to help calculate values and predict acceptable performance ...
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Feedback Compensation Equations This section highlights the design consideration for a voltage- mode controller requiring external compensation. To address a broad range of applications, a type-3 feedback network is recommended (see Figure 15 COMP ...
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It is recommended a mathematical model is used to plot the loop response. Check the loop gain against the error amplifier’s open-loop gain. Verify phase margin results and adjust as necessary. The following equations describe the frequency response of the ...
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For extreme cases (such as high current (>20A using parallel lower FETs) and low threshold (~1V)), one possible solution is to capacitive-couple the LGATE; Figure 18 shows one implementation. The ...
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Figure 20 shows the upper gate drive supplied by a direct connection to VCC12. This option should only be used in converter systems where the main input voltage is +5 VDC or less. The peak upper gate-to-source voltage is approximately ...
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Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function ...
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Snubbers A snubber network is a series resistor and capacitor, usually from the phase node to GND (across the lower FET used to dampen the ringing of the phase node, which can introduce noise into other parts of ...
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A comparator monitors the COMP pins, and if either one exceeds the trip point (nominal 3.3V), and stays above it for a filter time (1-2 clock pulses of the internal oscillator; 3-6µs at the nominal 300kHz; 2-4µs at 500kHz), ...
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PCB Layout Considerations General Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. ...
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IC, the more they will heat each other, so keep that thermal consideration in mind. BOOT1/2 capacitors should be near their pins; the bottom to phase and diode can be a little further away separate small capacitor ...
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... Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...