ISL6721AV Intersil, ISL6721AV Datasheet
ISL6721AV
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ISL6721AV Summary of contents
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... Ld SOIC (Note) ISL6721AV* ISL67 21AV -40 to +105 16 Ld TSSOP ISL6721AVZ* ISL67 21AVZ -40 to +105 16 Ld TSSOP (Note) *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets ...
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Functional Block Diagram VCC START/STOP UV COMPARATOR + ENABLE - + - BG LGND THERMAL PROTECTION RESTART DELAY ISET 0.8 ISENSE VREF + S 53µA + 100mV SLOPE 0 CLAMP + COMP - ERROR 2.5V ...
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Typical Application - 48V Input Dual Output Flyback, 3.3V @ 2.5A, 1.8V @ 1.0A VIN 36-75V C1 R2 VIN- SYNC VR1 3 ISL6721 C18 R24 C2 C5 CR6 C3 TP1 ...
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Typical Boost Converter Application Schematic L1 VIN+ C1 VIN- 4 ISL6721 CR1 R12 C12 GATE VC PGND ISENSE SYNC VCC SLOPE VREF UV LGND OV SS RTCT COMP ISET VFB R5 R11 R6 ...
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... CS 5 ISL6721 Thermal Information Thermal Resistance (Typical, Note SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Ld TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = V < 20V 11kΩ 330 pF +25°C. A TEST CONDITIONS MIN 7 ...
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Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic on page 2 and page 3. 9V < V Typical values are at T PARAMETER ERROR AMPLIFIER Open Loop Voltage Gain Gain-Bandwidth Product Reference ...
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Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic on page 2 and page 3. 9V < V Typical values are at T PARAMETER SOFT-START Charging Current Charged Threshold Voltage Initial Overcurrent Discharge ...
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Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic on page 2 and page 3. 9V < V Typical values are at T PARAMETER Undervoltage Hysteresis Voltage UV Bias Current OV Bias Current ...
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Pin Descriptions SLOPE - Means by which the ISENSE ramp slope may be increased for improved noise immunity or improved control loop stability for duty cycles greater than 50%. An internal current source charges an external capacitor to GND during ...
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The total supply current (I plus I ) will be higher depending on the load applied to GATE. Total current is the sum of the quiescent current and the average gate current. Knowing the operating frequency ...
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DOWNSLOPE Downslope CURRENT SENSE SIGNAL Current Sense Signal TIME Time FIGURE 5. The minimum amount of capacitance to place at the SLOPE pin is calculated in Equation 6: t – ×10 • C 4.24 ---------------------- - F = ...
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Ground Plane Requirements Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents associated with the output stage. Power ...
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Maximum Primary Inductance: • MIN ON MAX ( ) -------------------------------------------------------- - Lp max = = 43.3 I PPK Choose desired primary inductance to be 40µH. The core structure must be able to deliver ...
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To minimize the transformer leakage inductance, the primary was split into two sections connected in parallel and positioned such that the other windings were sandwiched between them. The output windings were configured so that the 1.8V winding is a tap ...
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Pgate Once the losses are known, the device package must be selected and the heatsinking method designed. ...
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The loop compensation is placed around the Error Amplifier (EA) on the secondary side of the converter. The primary side amplifier located in the control IC is used as a unity gain inverting amplifier and provides no loop compensation. A ...
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V , maximum load, maximum C IN minimum ESR. The higher the desired bandwidth of the converter, the more difficult create a solution that is stable over the entire operating range. A good rule of thumb ...
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OC fault threshold at which point the IC enters the fault shutdown mode. Trace 2 shows the behavior of the timing capacitor voltage during a shutdown fault. Most of the functions of the IC are de-powered during a fault, ...
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... Resistor, 1206, 1% 5.11 Resistor, 0603, 1% 3.92k Resistor, 2512, 1% 100 Resistor, 0603, 1% 1.00 Resistor, 2512, 1% 221k Resistor, 0603, 1% 75.0k Resistor, 0603, 1% OMIT Transformer, MIDCOM 31555 Opto-coupler, NEC PS2801-1 Shunt Reference, National LM431BIM3 PWM, Intersil ISL6721IB Zener, 15V, Zetex BZX84C15 DESCRIPTION March 5, 2008 FN9110.6 ...
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References 1. Ridley, R., “A New Continuous-Time Model for Current Mode Control”, IEEE Transactions on Power Electronics, Vol. 6, No. 2, April 1991. 2. Dixon, Lloyd H., “Closing the Feedback Loop”, Unitrode Power Supply Design Seminar, SEM-700, 1990. 20 ISL6721 ...
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Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX 0.25(0.010) E AREA E1 - 0.05(0.002) SEATING PLANE - -C- α 0.10(0.004) 0.10(0.004 NOTES: 1. These package ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...