LNBH23PPR STMicroelectronics, LNBH23PPR Datasheet - Page 14

IC LNB SUPPLY/CTRL POWERSSO-24

LNBH23PPR

Manufacturer Part Number
LNBH23PPR
Description
IC LNB SUPPLY/CTRL POWERSSO-24
Manufacturer
STMicroelectronics
Datasheet

Specifications of LNBH23PPR

Applications
Converter, Analog and Digital STB Receivers/SatTV
Voltage - Input
8 ~ 15 V
Number Of Outputs
1
Voltage - Output
13.4V, 18.5V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
PowerSSO-24
Output Voltage
25 V
Output Current
1000 mA
Input Voltage
8 V to 15 V
Switching Frequency
220 KHz
Operating Temperature Range
- 25 C to + 125 C
Mounting Style
Through Hole
Duty Cycle (max)
57 %
For Use With
497-8717 - DEMO BOARD BASED ON LNBH23497-8336 - BOARD EVAL BASED ON LNBH23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-6121-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LNBH23PPR
Manufacturer:
ST
Quantity:
8 000
Part Number:
LNBH23PPR
Manufacturer:
ST
0
Part Number:
LNBH23PPR
Manufacturer:
ST
Quantity:
20 000
Part Number:
LNBH23PPR-MYS
Manufacturer:
ST
Quantity:
20 000
Part Number:
LNBH23PPR/1B
Quantity:
2 500
Part Number:
LNBH23PPR/1B
Manufacturer:
ST
Quantity:
1 570
Part Number:
LNBH23PPR/1B
Manufacturer:
ST
0
Part Number:
LNBH23PPR/1B
Manufacturer:
ST
Quantity:
20 000
I²C bus interface
6
6.1
6.2
6.3
6.4
6.5
14/32
I²C bus interface
Data transmission from main MCU to the LNBH23 and vice versa takes place through the 2
wires I²C bus Interface, consisting of the 2 lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data validity
As shown in
of the clock. The HIGH and LOW state of the data line can only change when the clock
signal on the SCL line is LOW.
Start and stop condition
As shown in
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each START condition.
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
Acknowledge
The master (MCU) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
this clock pulse. The peripheral which has been addressed has to generate acknowledge
after the reception of each byte, otherwise the SDA line remains at the HIGH level during the
ninth clock pulse time. In this case the master transmitter can generate the STOP
information in order to abort the transfer. The LNBH23 won't generate acknowledge if the
V
Transmission without acknowledge
Avoiding to detect the acknowledges of the LNBH23, the MCU can use a simpler
transmission: simply it waits one clock cycle without checking the slave acknowledging, and
sends the new data. This approach of course is less protected from misworking and
decreases the noise immunity.
CC
supply is below the under voltage lockout threshold (6.7 V typ.).
Figure
Figure
Figure 6
7). The peripheral (LNBH23) that acknowledges has to pull-down (LOW)
5, the data on the SDA line must be stable during the high semi-period
a start condition is a HIGH to LOW transition of the SDA line while
Doc ID 13356 Rev 7
LNBH23

Related parts for LNBH23PPR