L6713ATR STMicroelectronics, L6713ATR Datasheet

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... Workstation and server CPU power supply ■ VRM modules Table 1. Device summary Order codes L6713A L6713ATR August 2008 and AMD 6 bit CPUs TQFP64 (Exposed pad) Description L6713A implements a two/three phase step-down controller with 180º/120º phase-shift between each phase with integrated high current drivers in a compact 10x10 mm body package with exposed pad ...

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Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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L6713A 12 Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 23 Tolerance band (TOB) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 23.1 Controller tolerance ...

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L6713A 1 Block diagram Figure 1. Block diagram SS_END / PGOOD OSC / FAULT SS/ LTBG/ AMD VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 / D-VID VID_SEL HS1 LS1 HS2 LOGIC PWM LOGIC PWM ADAPTIVE ANTI ADAPTIVE ANTI CROSS ...

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Pin settings 2 Pin settings 2.1 Pin connection Figure 2. Pin connection (top view) TM SGND N.C. N.C. N.C. PGND2 LGATE2 VCCDR2 VCCDR3 LGATE3 PGND3 PGND1 LGATE1 VCCDR1 PHASE1 N.C. 6/ ...

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L6713A 2.2 Pin description Table 2. Pin description N° Pin 1 UGATE1 2 BOOT1 3 N.C. 4 PHASE3 5 UGATE3 6 BOOT3 7 N.C. 8 PHASE2 9 UGATE2 10 BOOT2 11 N.C. 12 N.C. 13 N.C. 14 N.C. 15 VCC ...

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Pin settings Table 2. Pin description (continued) N° Pin 17 OUTEN 18 LTB 19 SGND 20 VSEN 21 DROOP COMP 24 N.C. 25 N.C. 26 CS2+ 27 CS2- 28 CS3+ 29 CS3- 8/64 Output enable pin. Internally ...

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L6713A Table 2. Pin description (continued) N° Pin 30 CS1+ 31 CS1- SS/ LTBG/ 32 AMD 33 OVP 34 VID_SEL 35 OCSET 36 FBG OSC/ 37 FAULT 38 VID7/DVID 39 VID6 Channel 1 current sense positive input. Connect through an ...

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Pin settings Table 2. Pin description (continued) N° Pin 40 to VID5 to 45 VID0 SS_END/ 46 PGOOD 47 VR_HOT 48 VR_FAN SGND 51 N.C. 52 N.C. 53 N.C. 54 PGND2 55 LGATE2 10/64 Intel mode. Voltage ...

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L6713A Table 2. Pin description (continued) N° Pin 56 VCCDR2 57 VCCDR3 58 LGATE3 59 PGND3 60 PGND1 61 LGATE1 62 VCCDR1 63 PHASE1 64 N.C. Thermal PAD pad Channel 2 LS driver supply. It must be connected to others ...

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Electrical data 3 Electrical data 3.1 Maximum ratings Table 3. Absolute maximum ratings Symbol CCDRx BOOTx PHASEx UGATEx PHASEx BOOTx V PHASEx 3.2 Thermal data Table ...

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L6713A 4 Electrical characteristics ± Table 5. Electrical characteristics Symbol Parameter Supply current I VCC supply current CC I VCCDRx supply current CCDRx I BOOTx supply current BOOTx Power-ON VCC turn-ON UVLO ...

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Electrical characteristics Table 5. Electrical characteristics (continued) Symbol Parameter Reference and DAC k Output voltage accuracy VID V Boot voltage BOOT VID pull-up current I VID VID pull-down current VID IL VID thresholds VID IH VID_SEL threshold (Intel mode) VID_SEL ...

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L6713A Table 5. Electrical characteristics (continued) Symbol Parameter t LS rise time RISE_LGATEx I LS source current LGATEx R LS sink resistance LGATEx Protections Over voltage protection OVP (VSEN rising) I current Program- OVP mable OVP Comparator offset voltage Preliminary ...

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VID Tables 5 VID Tables 5.1 Mapping for the Intel VR11 mode Table 6. Voltage identification (VID) mapping for Intel VR11 mode VID7 VID6 800 mV 400 mV 5.2 Voltage identification (VID) for Intel VR11 mode Table 7. Voltage identification ...

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L6713A Table 7. Voltage identification (VID) for Intel VR11 mode Output HEX code voltage ( 1.46875 1 8 1.46250 1 9 1.45625 1 A 1.45000 1 B 1.44375 1 C 1.43750 1 D 1.43125 1 E 1.42500 1 ...

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VID Tables Table 7. Voltage identification (VID) for Intel VR11 mode Output HEX code voltage ( 1.26250 3 9 1.25625 3 A 1.25000 3 B 1.24375 3 C 1.23750 3 D 1.23125 3 E 1.22500 3 F 1.21875 ...

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L6713A Table 8. Voltage identifications (VID) for Intel VR10 mode + 6.25 mV VID VID VID VID ...

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VID Tables Table 8. Voltage identifications (VID) for Intel VR10 mode + 6.25 mV VID VID VID VID ...

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L6713A Table 10. Voltage identifications (VID) codes for AMD 6 bit mode VID5 VID4 VID3 VID2 VID1 ...

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Reference schematic 6 Reference schematic Figure 3. Reference schematic - Intel VR10.x, VR11 - 3-phase operation V IN GND IN to SSEND R VID_SEL OUTEN C LTB R LTB L6713A ...

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L6713A Figure 4. Reference schematic - Intel VR10.x, VR11 - 2-phase operation V IN GND IN to SSEND R SSOSC VID_SEL OUTEN C LTB R LTB L6713A REF.SCH: Intel Mode ...

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Reference schematic Figure 5. Reference schematic - AMD 6 bit - 3-phase operation V IN GND IN OUTEN C LTB R LTB L6713A REF.SCH: AMD Mode - 3-Phase Operation 24/64 ...

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L6713A Figure 6. Reference schematic - AMD 6 bit - 2-phase operation V IN GND IN OUTEN C LTB R LTB L6713A REF.SCH: AMD Mode - 2-Phase Operation L IN ...

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Device description 7 Device description L6713A is two/three phase PWM controller with embedded high current drivers providing complete control logic and protections for a high performance step-down DC-DC voltage regulator optimized for advanced microprocessor power supply. Multi phase buck is ...

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L6713A L6713A provides a programmable over-voltage protection to protect the load from dangerous over stress. It can be externally set to a fixed voltage through an apposite resistor can be set internally, latching immediately by turning ON the ...

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Configuring the device 8 Configuring the device Number of phases and multiple DACs need to be configured before the system starts-up by programming the apposite pin PHASE_SEL and SS/LTBG/AMD pin. The configuration of this pin identifies two main working areas ...

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L6713A Output voltage is programmed through the VID pins: they are inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a multiplexer ...

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Power dissipation 9 Power dissipation L6713A embeds high current MOSFET drivers for both high side and low side MOSFETs then important to consider the power the device is going to dissipate in driving them in order to avoid ...

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L6713A Figure 7. L6713A dissipated power (quiescent + switching) 2-PHASE Operation; Rgate=0; Rmosfet=0 4500 HS=1xSTD38NH02L; LS=1xSTD90NH02L HS=2xSTD38NH02L; LS=2xSTD90NH02L 4000 HS=1xSTD55NH2LL; LS=1xSTD95NH02L 3500 HS=2xSTD55NH2LL; LS=2xSTD95NH02L HS=3xSTD55NH22L; LS=3xSTD95NH02L 3000 2500 2000 1500 1000 500 0 50 150 250 350 450 550 Switching ...

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Current reading and current sharing loop 10 Current reading and current sharing loop L6713A embeds a flexible, fully-differential current sense circuitry that is able to read across inductor parasitic resistance or across a sense resistor placed in series to the ...

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L6713A The Rg trans-conductance resistor has to be selected using the following formula, in order to guarantee the correct functionality of internal current reading circuitry: Current sharing control loop reported in the current delivered by each phase and the average ...

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Differential remote voltage sensing 11 Differential remote voltage sensing The output voltage is sensed in fully-differential mode between the FB and FBG pin. The FB pin has to be connected through a resistor to the regulation point while the FBG ...

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L6713A 12 Voltage positioning Output voltage positioning is performed by selecting the reference DAC and by programming the droop function and offset to the reference sourced from DROOP and sunk from VSEN pins cause the output voltage to vary according ...

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Voltage positioning 12.2 Droop function (Optional) This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current: a static error proportional to the ...

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L6713A 13 Load transient boost technology Load transient boost LTB Technology™ (patent pending L6713A feature to minimize the count of output filter capacitors (MLCC and bulk capacitors) to respect the load transient specifications. The device turns on simultaneously ...

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Load transient boost technologyTM 13.1 LTB™ gain modification (Optional) The internal gain can be modified through the SS/LTBG/AMD pin, as shown in the Figure 13. The SS/LTBG/AMD pin is also used to set the soft-start time, so the current flowing ...

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L6713A 14 Dynamic VID transitions The device is able to manage dynamic VID Code changes that allow output voltage modification during normal device operation. OVP and UVP signals (and PGOOD in case of AMD mode) are masked during every VID ...

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Dynamic VID transitions Figure 14. Dynamics VID transitions VID Clock VID [0,7] Int. Reference V out 40/64 T DVID VID x 4 Step VID Transition Step VID Transition Vout Slope Controlled by internal Vout ...

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L6713A 15 Enable and disable L6713A has three different supplies: VCC pin to supply the internal control logic, VCCDRx to supply the low side drivers and BOOTx to supply the high side drivers. If the voltage at pins VCC and ...

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Soft-start 16 Soft-start L6713A implements a soft-start to smoothly charge the output filter avoiding high in-rush currents to be required to the input power supply. The device increases the reference from zero up to the programmed value in different ways ...

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L6713A Protections are active during soft-start, UVP is enabled after the reference reaches 0.6V while OVP is always active with a fixed 1.24V threshold before V coming from the VID (or the programmed V Figure 15). Note: If during T ...

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Soft-start Figure 17. Soft-start time for Intel mode when using R 16.1.2 SS/LTB/AMD connections when using LTB™ gain < 2 When using LTB™ gain <2, the equivalent because until the soft-start is not finished the Q ...

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L6713A Figure 19. Soft-start time for Intel mode when using R 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 16.2 AMD mode Once L6713A receives all the correct supplies and enables, and AMD mode has been selected, ...

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Soft-start 16.3 Low-side-less startup In order to avoid any kind of negative undershoot on the load side during start-up, L6713A performs a special sequence in enabling LS driver to switch: during the soft-start phase, the LS driver results disabled (LS ...

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L6713A 17 Output voltage monitor and protections L6713A monitors through pin VSEN the regulated voltage in order to manage the OVP, UVP and PGOOD (when applicable) conditions. The device shows different thresholds when programming different operation mode (Intel or AMD, ...

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Output voltage monitor and protections Figure 22. Output voltage protections and typical principle connections (OUTEN = Preliminary OVP VSEN Monitored UVLO VCC UVLO OVP 17.3 Over voltage and programmable OVP Once VCC crosses the turn-ON threshold and ...

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L6713A 18 Over current protection The device limits the total delivered current turning OFF all the MOSFETs as soon as the delivery current is higher than an adjustable thresholds.This condition is lathed and power supply or OUTEN pin cycling is ...

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Oscillator 19 Oscillator L6713A embeds two/three phase oscillator with optimized phase-shift (180º/120º phase- shift) in order to reduce the input rms current and optimize the output filter definition. The internal oscillator generates the triangular waveform for the PWM charging and ...

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L6713A 20 Driver section The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the equivalent R The drivers for the high-side MOSFETs use BOOTx pins for supply and PHASEx pins for return. The ...

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System control loop compensation 21 System control loop compensation The control loop is composed by the current sharing control loop average current mode control loop. Each loop gives, with a proper gain, the correction to the PWM in order to ...

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L6713A Removing the dependence from the error amplifier gain, so assuming this gain high enough, and with further simplifications, the control loop gain results LOOP The system control loop gain to minimize static error and to ...

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Thermal monitor 22 Thermal monitor L6713A continuously senses the system temperature through TM pin: depending on the voltage sensed by this pin, the device sets free the VR_FAN pin as a warning and, after further temperature increase, also the VR_HOT ...

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L6713A 23 Tolerance band (TOB) definition Output voltage load-line varies considering component process variation, system temperature extremes, and age degradation limits. Moreover, individual tolerance of the components also varies among designs then possible to define a manufacturing tolerance ...

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Tolerance band (TOB) definition 23.2 Ext. current sense circuit tolerance (TOB It can be further sliced as follow: ● Inductor DCR Tolerance (k voltage since the device reads a current that is different from the real current flowing into the ...

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L6713A 23.4 Temperature measurement error (V Error in the measured temperature (for thermal compensation) impacts on the output regulated voltage since the correction form the compensation circuit is not what required to keep the output voltage flat. The measurement error ...

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Layout guidelines 24 Layout guidelines Since the device manages control functions and high-current drivers, layout is one of the most important things to consider when designing such high current applications. A good layout solution can generate a benefit in lowering ...

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L6713A 24.2 Small signal components and connections These are small signal components and connections to critical nodes of the application as well as bypass capacitors for the device supply capacitor (VCC, VCCDRx and Bootstrap capacitor) close to the device and ...

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Embedding L6713A - based VR 25 Embedding L6713A - based VR When embedding the VRD into the application, additional care must be taken since the whole VRD is a switching DC/DC regulator and the most common system in which it ...

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L6713A 26 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the ...

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Package mechanical data Table 15. TQFP64 mechanical data Dim ccc Figure 29. Package dimensions 62/64 mm. Min. Typ. Max. 1.20 0.05 0.15 0.95 ...

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L6713A 27 Revision history Table 16. Document revision history Date 03-Mar-2006 07-Nov-2006 04-Aug-2008 Revision 1 Initial release. Updated D2 and E2 exposed tab measures in 2 mechanical data Updated Table 2 on page 3 page 48, Section 19 on page ...

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