ISL6425ERZ Intersil, ISL6425ERZ Datasheet

ISL6425ERZ

Manufacturer Part Number

ISL6425ERZ

Description

IC REG DUAL LNBP TTL-INP 32-QFN

Manufacturer

Intersil

Datasheet

1.ISL6425ERZ.pdf (12 pages)

Specifications of ISL6425ERZ

Applications

Converter, Satellite Set-Top Box Designs

Voltage - Input

8 ~ 14 V

Number Of Outputs

Voltage - Output

13 ~ 18 V

Operating Temperature

-20°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

ISL6425ERZ

Manufacturer:

INTERSIL

Quantity:

101

Current page: 1 of 12
Download datasheet (286Kb)

Single Output LNB Supply and Control

Voltage Regulator with I

Advanced Satellite Set-top Box Designs

The ISL6425 is a highly integrated solution for supplying

power and control signals from advanced satellite set-top

box (STB) modules to the low noise block (LNB). This device

is comprised of a current-mode boost PWM and a low-noise

linear regulator, along with the circuitry required for I

device interfacing and for providing DiSEqC standard control

signals to the LNB.

A regulated output voltage is available at the output terminal

(VOUT) to support the operation of the antenna port in

advanced satellite STB applications. The regulated output

may be set to either 13V or 18V by use of the voltage select

command (VSEL) through the I

compensate for the voltage drop in the coaxial cable, the

voltage may be increased by 1V with the line length

compensation (LLC) feature. An enable command sent on

the I

linear combination, disabling the output to conserve power.

A current-mode boost converter provides the linear regulator

with an input voltage that is set to the required output

voltage, plus 1.2V (typ.) to insure minimum power

dissipation. This maintains a constant voltage drop across

the linear pass element, while permitting an adequate

voltage range for tone injection.

The device is capable of providing 750mA (typ.).

Ordering Information

NOTE: Intersil Pb-free products employ special Pb-free material sets;

molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with

both SnPb and Pb-free soldering operations. Intersil Pb-free products

are MSL classified at Pb-free peak reflow temperatures that meet or

exceed the Pb-free requirements of IPC/JEDEC J STD-020.

ISL6425ER

ISL6425ER-T

ISL6425ERZ

(Note)

ISL6425ERZ-T

(Note)

PART NUMBER

C bus provides standby mode control for the PWM and

32 Ld 5x5 QFN Tape and Reel

(Pb-free)

RANGE (°C)

-20 to 85

TEMP.

C bus. Additionally, to

32 Ld 5x5 QFN L32.5x5

32 Ld 5x5 QFN

(Pb-free)

C Interface for

Data Sheet

PACKAGE

L32.5x5

DWG. #

PKG.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Features

• Switch-Mode Power Converter for Lowest Dissipation

• External Pin to Select 13V/18V Options

• DSQIN and SEL18V pins are 2.5V logic compatible

• I

• Built-In Tone Oscillator Factory Trimmed to 22kHz

• Internal Over-Temperature Protection and Diagnostics

• Internal Overload and Overtemp Flags (Visible on I

• LNB Short-Circuit Protection and Diagnostics

• QFN Package

• Pb-free available (RoHS Compliant)

Applications

• LNB Power Supply and Control for Satellite Set-Top Box

References

• Tech Brief 389 (TB389) - “PCB Land Pattern Design and

- Boost PWM with >92% Efficiency

- Selectable 13V or 18V Outputs

- Digital Cable Length Compensation (1V)

- Registered Slave Address 0001 00XX

- Fully Functional 3.3V, 5V Operation up to 400kHz

- Facilitates DiSEqC (EUTELSAT) Encoding

- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat

- Near Chip-Scale Package Footprint

Surface Mount Guidelines for QFN Packages”; Available

on the Intersil website, www.intersil.com

C Compatible Interface for Remote Device Control

No Leads - Product Outline

February 8, 2005

All other trademarks mentioned are the property of their respective owners.

Intersil (and design) is a trademark of Intersil Americas Inc.

ISL6425

FN9176.1

Related parts for ISL6425ERZ

ISL6425ERZ Summary of contents

Page 1

... Ld 5x5 QFN Tape and Reel ISL6425ERZ - 5x5 QFN (Note) (Pb-free) ISL6425ERZ 5x5 QFN Tape and Reel (Note) (Pb-free) NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...

Page 2

Pinout SEL18V BYPASS 2 ISL6425 ISL6425 (32 LEAD 5x5 QFN) TOP VIEW PGND SGND PGND 7 GATE ...

Page 3

Typical Application Schematic VIN 56uF 33uH FDS6612A 100 0.1 C2 100pF 4.7uH 1 C4 C13 ...

Page 4

Block Diagram OVERCURRENT COUNTER PROTECTION LOGIC SCHEME 1 PWM LOGIC GATE PGND E PAD ILIM CS AMP CS ∑ 11 COMPENSATION COMP VSW 14 VOUT 20 ON CHIP VCC 28 LINEAR UVLO SGND POR ...

Page 5

Absolute Maximum Ratings Supply Voltage 8.0V to 18.0V CC Logic Input Voltage Range ...

Page 6

Electrical Specifications V = 12V ENT = L, DCL = L, DSQIN = L, I access to the system. (Continued) PARAMETER LINEAR REGULATOR Drop-Out Voltage DSQIN, SEL18V INPUT PINs (Note 6) Asserted Low Asserted HIGH Input Current CURRENT ...

Page 7

Functional Pin Description SYMBOL SDA Bidirectional data from/to I SCL Clock from I VSW Input of the linear post-regulator. PGND Dedicated ground for the output gate driver of the PWM. CS Current sense input; connect Rsc at this pin for ...

Page 8

Output Timing The programmed output voltage rise and fall times can be set by an external capacitor. The output rise and fall times will be approximately 3400 times the TCAP value. For the recommended range of 0.47µF to 2.2µF, the ...

Page 9

SDA SCL S START CONDITION FIGURE 2. START AND STOP WAVEFORMS Byte Format Every byte put on the SDA line must be 8 bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has ...

Page 10

TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION SR1 DCL ISEL1 ENT1 LLC1 ...

Page 11

Once Vcc rises above the UVLO level, the POWER OK 2 signal given to the I C interface block will be HIGH, the I interface becomes operative and the SR can be configured by the main microprocessor. About 400mV of ...

Page 12

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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