ISL6425ERZ Intersil, ISL6425ERZ Datasheet - Page 7

• Manufacturer Part Number: ISL6425ERZ
• Description: IC REG DUAL LNBP TTL-INP 32-QFN
• Manufacturer: Intersil

Specifications of ISL6425ERZ

• Applications: Converter, Satellite Set-Top Box Designs
• Voltage - Input: 8 ~ 14 V
• Number Of Outputs: 2
• Voltage - Output: 13 ~ 18 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Pin Description
Functional Description
The ISL6425 single output voltage regulator makes an ideal
choice for advanced satellite set-top box and personal video
recorder applications. Both supply and control voltage
outputs for a low noise block (LNB) are available
simultaneously in any output configuration. The device
utilizes a built-in DC/DC step-converter that, from a single
supply source ranging from 8V to 14V, generates the voltage
that enables the linear post-regulator to work with a
minimum of dissipated power. An undervoltage lockout
circuit disables the circuit when V
threshold (7.5V typ).
DiSEqC Encoding
The internal oscillator is factory-trimmed to provide a tone of
22kHz in accordance with DISeqC standards. No further
adjustment is required. The 22kHz oscillator can be
controlled either by the I
dedicated pin (DSQIN) that allows immediate DiSEqC data
encoding for the LNB. All the functions of this IC are
controlled via the I
(SR). The same registers can be read back, and two bits will
report the diagnostic status. The internal oscillator operates
the converters at ten times the tone frequency. The device
offers full I
400kHz operation.
If the Tone Enable (ENT) bit is set LOW through I
the DSQIN terminal activates the internal tone signal,
CPVOUT, CPSWIN, CPSWOUT Charge pump connections.
SYMBOL
2
BYPASS
SEL18V
DSQIN
COMP
PGND
SGND
AGND
ADDR
C compatible functionality, 3.3V or 5V, and up to
TCAP
VOUT
GATE
VSW
VCC
SDA
SCL
CS
FB
2
C bus by writing to the system registers
2
C interface (ENT bit) or by a
Bidirectional data from/to I
Clock from I
Input of the linear post-regulator.
Dedicated ground for the output gate driver of the PWM.
Current sense input; connect Rsc at this pin for desired overcurrent value for the PWM.
Small signal ground for the IC.
Analog ground for the IC.
Capacitor for setting rise and fall time of the output of the LNB. Use a capacitor value of 1µF or higher.
Bypass capacitor for internal 5V.
When HIGH this pin enables the internal 22kHz modulation for the LNB, Use this pin for tone enable function for
the LNB.
Main power supply to the chip.
This is the device output of the PWM. This high current driver output is capable of driving the gate of a power FET.
This output is actively held low when Vcc is below the UVLO threshold.
Output voltage for the LNB.
Address pin to select two different addresses per voltage level at this pin.
Error amp output used for compensation.
Feedback pin for the PWM.
When connected HIGH, this pin will change the output of the PWM to 18V.
7
CC
drops below a fixed
2
C bus.
2
C, then
2
C bus.
ISL6425
modulating the dc output with a 0.3V, 22kHz, symmetrical
waveform. The presence of this signal usually gives the LNB
information about the band to be received.
Burst coding of the 22kHz tone can be accomplished due to
the fast response of the DSQIN input and rapid tone
response. This allows implementation of the DiSEqC
(EUTELSAT) protocols.
When the ENT bit is set HIGH, a continuous 22kHz tone is
generated regardless of the DSQIN pin logic status. The
ENT bit must be set LOW when the DSQIN pin is used for
DiSEqC encoding.
Linear Regulator
The output linear regulator will sink and source current. This
feature allows full modulation capability into capacitive loads
as high as 0.25µF. In order to minimize the power
dissipation, the output voltage of the internal step-up
converter is adjusted to allow the linear regulator to work at
minimum dropout.
When the device is put in the shutdown mode (EN = LOW),
the PWM power block is disabled. When the regulator block
is active (EN = HIGH), the output can be logic controlled to
be 13V or 18V (typical) by means of the VSEL bit (Voltage
Select) for remote controlling of non-DiSEqC LNBs.
Additionally, it is possible to increment by 1V (typical) the
selected voltage value to compensate for the excess voltage
drop along the coaxial cable (LLC bit HIGH).
FUNCTION
February 8, 2005
FN9176.1