MAX17082GTL+ Maxim Integrated Products, MAX17082GTL+ Datasheet - Page 17

• Manufacturer Part Number: MAX17082GTL+
• Description: IC CTLR PWM DUAL IMVP-6.5 40TQFN
• Manufacturer: Maxim Integrated Products
• Series: Quick-PWM™r

Specifications of MAX17082GTL+

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 4.5 ~ 5.5 V
• Number Of Outputs: 1
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Lead Free Status / Rohs Status: Details

PIN
20
21
22
23
24
25
26
27
28
29
30
31
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
(MAX17021)
(MAX17082/
MAX17482)
PHASEGD
NAME
BST2
BST1
DH2
DH1
LX2
DL2
V
DL1
LX1
DD
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Phase-Good Current-Balance Open-Drain Output. Used to signal the system that one of the two
phases either has a fault condition or is not matched with the other. Detection is done by identifying
the need for a large on-time difference between phases in order to achieve or move towards current
balance. PHASEGD is low in shutdown.
PHASEGD is forced high impedance whenever the slew-rate controller is active (output-voltage
transitions).
PHASEGD is forced high impedance while in one-phase operation (DPRSLPVR = high or
Boost Flying-Capacitor Connection for Phase 2. BST2 provides the upper supply rail for the DH2 high-
side gate driver. An internal switch between V
side MOSFET is on (DL2 pulled high and LX2 pulled to ground).
Inductor Connection for Phase 2. LX2 is the internal lower supply rail for the DH2 high-side gate driver.
Also used as an input to the controller’s zero-crossing comparator for phase 2.
High-Side Gate-Driver Output for Phase 2. DH2 swings from LX2 to BST2. The controller pulls DH2 low
in shutdown.
Low-Side Gate-Driver Output for Phase 2. DL2 swings from GND to V
after detecting an inductor current zero crossing. DL2 is forced low during one-phase operation (
GND or CSP2 = V
Open-Drain Output of Internal Comparator.
1.5V (30% of V
Driver Supply Voltage Input. V
drivers and refresh the BST_ flying capacitors during the off-times. Connect V
system supply voltage. Bypass V
capacitor.
Low-Side Gate-Driver Output for Phase 1. DL1 swings from GND to V
overvoltage fault is detected, overriding any negative current-limit condition that might be present. DL1 is
forced low after soft-shutdown or in skip mode after detecting an inductor current zero crossing.
High-Side Gate-Driver Output for Phase 1. DH1 swings from LX1 to BST1. The controller pulls DH1 low
in shutdown.
Inductor Connection for Phase 1. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
Also used as an input to the controller’s zero-crossing comparator for phase 1.
Boost Flying-Capacitor Connection for Phase 1. BST1 provides the upper supply rail for the DH1 high-
side gate driver. An internal switch between V
side MOSFET is on (DL1 is pulled high and LX1 is pulled to ground).
IMVP-6+ Slew-Rate Select Input. This 1.0V logic input signal from the IMVP-6+ system is usually the
logical complement of the DPRSLPVR signal. However, the IMVP-6+ specification supports a special
slow C4 exit condition that allows both
When this occurs, the voltage-transition slew rate reduces to 1/4 the nominal (R
for the duration of this logic condition. The slew rate returns to normal when either DPRSLPVR or
IMVP-6.5 Slew-Rate Select Input. This 1.0V logic input signal selects between the nominal and “slow”
(half of nominal rate) slew rates. When
the TIME resistance as defined above. When
nominal slew rate.
DPRSLPVR DPRSTP
is pulled low:
0
0
1
1
CC
).
CC
).
0
1
0
1
is high impedance in shutdown.
DD
is the supply voltage used to internally power the low-side gate
SLEW RATE
Nominal slew rate
Nominal slew rate
Nominal slew rate
Slew rate reduced to 1/4 of nominal
DD
to the system power ground with a 1μF each or greater ceramic
is forced high, the selected nominal slew rate is set by
FUNCTION
DD
DD
and DPRSLPVR to be pulled high simultaneously.
and BST2 charges the flying capacitor while the low-
and BST1 charges the flying capacitor while the low-
is pulled low when the voltage at THRM goes below
is forced low, the slew rate is reduced to half the
Pin Description (continued)
DD
DD
. DL1 is forced high when an output
. DL2 is forced low in skip mode
DD
TIME
to the 4.5V to 5.5V
-based) slew rate
= low).
=
17