ADP3157JR Analog Devices Inc, ADP3157JR Datasheet - Page 9

• Manufacturer Part Number: ADP3157JR
• Description: IC CNTRL SYNC PENTIUM III 16SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADP3157JR

• Rohs Status: RoHS non-compliant
• Applications: Controller, Intel Pentium® III
• Voltage - Input: 12V
• Number Of Outputs: 1
• Voltage - Output: 1.3 ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)

The maximum rms current of the low side FET is:
The R
dissipation. If 5% of the maximum output power is allowed for
FET dissipation, the total dissipation will be:
Allocating half of the total dissipation for the high side FET and
half for the low side FET, the required minimum FET resis-
tances will be:
Note that there is a trade-off between converter efficiency and
cost. Larger FETs reduce the conduction losses and allow
higher efficiency, but increase the system cost. If efficiency is
not a major concern, the International Rectifier IRL3803 is an
economical choice for both the high side and low side positions.
Those devices have an R
+25 C. The low side FET is turned on with at least 10 V. The
high side FET, however, is turned on with only 12 V – 5 V = 7 V.
The specified R
temperature of +140 C must be modified by:
Using this multiplier, the expected R
6 m = 10 m .
The high side FET dissipation is:
where the second term represents the turn-off loss of the FET.
(In the second term, Q
the gate for turn-off and I
sheet, Q
by the ADP3157 is about 1 A.)
The low side FET dissipation is:
(Note that there are no switching losses in the low side FET.)
To maintain an acceptable MOSFET junction temperature,
proper heat sinks should be used. The Thermalloy 6030 heat
sink has a thermal impedance of 13 C/W with convection cool-
ing. With this heat sink, the junction-to-ambient thermal imped-
ance of the chosen high side FET
sink-to-ambient) + 2 C/W (junction-to-case) + 0.5 C/W (case-
to-heat sink) = 15.5 C/W.
At full load, and at +50 C ambient temperature, the junction
temperature of the high side FET is:
The same heat sink may be used for the low side FET, e.g., the
Thermalloy type 7141 ( = 20.3 C/W). With this heat sink, the
junction temperature of the low side FET is:
REV. A
I
= 12.5 A rms
R
R
P
RMSLS
DFETHS
DS(ON)HSF(MIN)
DS(ON)LSF(MIN)
DS(ON)
GS
= [D
= I
is a 41 nC and the peak gate drive current provided
T
T
for each FET can be derived from the allowable
JLSMAX
MAXLF
RMSHS
JHSMAX
P
P
DS(ON)
DFETLS
FETALL
= 0.85 W/(12.5 A)
= 0.85 W/(11.6 A)
2
(I
R
= T
= T
LVALLEY
DS(ON)
at the expected highest FET junction
GS
= I
= 0.05 V
A
R
DS(ON)
A
G
is the gate charge to be removed from
DS(ON)MULT
+
RMSLS
+
is the gate current. From the data
+ 0.5 V
2 + I
JALS
JAHS
of 6 m at V
2
O
R
LPEAK
P
I
DS(ON)
OMAX
P
DFETLS
JAHS
IN
DFETHS
2
2
DS(ON)
= 1.7
I
= 5.5 m
= 6 m
2 + I
LPEAK
will be 13 C/W (heat
= 1.7 W
= 1.6 W
= +82.5 C
LVALLEY
at +140 C is 1.7
= +86 C
Q
GS
G
f
= 10 V and at
MIN
I
/I
LPEAK
G
~ 2.3 W
)/3]
0.5
–9–
All of the above-calculated junction temperatures are safely
below the +175 C maximum specified junction temperature of
the selected FETs.
The maximum operating junction temperature of the ADP3157
is calculated as follows:
where
ADP3157 and P
is equal to 110 C/W and I
follows:
The result is:
C
In continuous inductor-current mode, the source current of the
high side MOSFET is a square wave with a duty ratio of V
V
capacitors with low equivalent series resistance (ESR) and ad-
equate ripple-current rating must be connected across the input
terminals. The maximum rms current of the input bypass ca-
pacitors is:
For an FA-type capacitor with 2700 F capacitance and
10 V voltage rating, the ESR is 34 m and the allowed ripple
current at 100 kHz is 1.94 A. At +105 C, at least four such
capacitors must be connected in parallel to handle the calculated
ripple current. At +50 C ambient, however, a higher ripple
current can be tolerated, so three capacitors in parallel are
adequate.
The ripple voltage across the three paralleled capacitors is:
To further reduce the effect of the ripple voltage on the system
supply voltage bus and to reduce the input-current di/dt to
below the recommended maximum of 0.1 A/ s, an additional
small inductor (L > 1.7 H @ 10 A) should be inserted between
the converter and the supply bus (see Figure 2).
Feedback Loop Compensation Design for Active Voltage
Positioning
Optimized compensation of the ADP3157 allows the best pos-
sible containment of the peak-to-peak output voltage deviation.
Any practical switching power converter is inherently limited by
the inductor in its output current slew rate to a value much less
than the slew rate of the load. Therefore, any sudden change of
load current will initially flow through the output capacitors,
and this will produce an output voltage deviation equal to the
ESR of the output capacitor array times the load current change.
lN
IN
V
100 mV p-p
. To keep the input ripple voltage at a low value, one or more
CINRPL
Selection and Input Current di/dt Reduction
JA
is the junction-to-ambient thermal impedance of the
= I
P
DR
OMAX
T
= (C
I
DR
JICMAX
CINRMS
[ESR
is the drive power. From the data sheet,
RSS
= T
T
= 0.5 I
IN
+ C
JICMAX
IC
/3 +D
A
ISS
= 2.7 mA. P
+
)V
OMAX
= +86 C
MAXHF
JA
CC
(I
2
IC
= 8.5 A rms
f
MAX
V
/(3 C
CC
DR
= 307 mW
+ P
IN
can be calculated as
ADP3157
f
DR
MIN
)
)] =
OUT
JA
/