LTC1771IS8 Linear Technology, LTC1771IS8 Datasheet - Page 12

• Manufacturer Part Number: LTC1771IS8
• Description: IC CTRLR DC/DC STEPDOWN HE 8SOIC
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC1771IS8

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.23 ~ 18 V
• Current - Output: 5A
• Voltage - Input: 2.8 ~ 18 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Frequency - Switching: -

APPLICATIO S I FOR ATIO
LTC1771
2. Is the 0.1 F input decoupling capacitor closely con-
3. Does the V
4. Is the 1000pF decoupling capacitor for the current
5. Is the (+) plate of C
6. Are the signal and power grounds segregated? The
7. Keep the switching node (SW) and the gate node
12
nected between V
capacitor carries the high frequency peak currents.
resistors? The resistive divider R1 and R2 must be
connected between the (+) plate of C
ground. Locate the feedback resistors right next to the
LTC1771. The V
nodes with high slew rates.
sense resistor connected as close as possible to Pins 6
and 7? Ensure accurate current sensing with Kelvin
connections to the sense resistor.
resistor ? This capacitor provides the AC current to the
MOSFET.
signal ground consists of the (–) plate of C
the LTC1771 and the resistive divider. The power ground
consists of the Schottky diode anode and the (–) plate
of C
possible.
(PGATE) away from sensitive small signal nodes, espe-
cially the voltage sensing feedback pin (V
mize their PC trace area.
C
R1
SS
R2
C
ITH
IN
BOLD LINES INDICATE HIGH CURRENT PATHS
which should have as short lead lengths as
R
ITH
Figure 5. LTC1771 Layout Diagram
C
FF
1
2
3
4
FB
RUN/SS
I
V
GND
TH
FB
pin connect directly to the feedback
FB
U
LTC1771
IN
line should not be routed close to any
0.1 F
IN
(Pin 6) and ground (Pin 4)? This
SENSE
PGATE
closely connected to the sense
MODE
U
V
IN
8
7
6
5
MODE
W
+
+
OUT
C
C
FB
IN
OUT
OUT
), and mini-
D1
and signal
U
, Pin 4 of
Q1
L
1771 F05
V
OUT
Design Example
As a design example, assume V
15V
tion, we can easily calculate all the important components.
To optimize low current efficiency, MODE pin is tied to V
to enable Burst Mode operation, thus the minimum induc-
tance necessary is:
15 H is chosen for the application.
For the feedback resistors, choose R1 = 1M to minimize
supply current. R2 can then be calculated to be:
Assume that the MOSFET dissipation is to be limited to
P
If T
83 C/W, then the junction temperatures will be 91 C and
be calculated:
Since the gate of the MOSFET will see the full input voltage,
a MOSFET must be selected whose V
P-channel MOSFET that meets both the V
R
The most stringent requirement for the Schottky diode
occurs when V
V
P
P
IN
DS(ON)
R
L
R2 = (V
= 0.33. The required R
P
P
= 0.25W.
. In this case the worst-case dissipation rises to:
A
MIN
(MAX)
D
SENSE
I
- Channel R
= 70 C and the thermal resistance of the MOSFET is
L
= 70 H(3.3V + 0.5)(0.05 ) = 13.3 H
I
requirement is the Si6447DQ.
SC AVG
, V
3 5
= 100mV/2A = 0.05
OUT
.
(
OUT
/1.23 – 1) • R1 = 1.68M
s
OUT
)
= 3.3V, and I
3 3
DS(ON)
V
.
D
= 0V (i.e., short circuit) at maximum
15
V
V
IN
0 5
H
DS(ON)
V
.
0 130
IN
.
V
3 3
10
V
MAX
.
D
V
V
IN
for the MOSFET can now
= 2A. With this informa-
0 89
= 10V (nominal), V
.
0 5
0 5
.
0 25
.
A
.
V
V
GS(MAX)
W
2
A
GS(MAX)
2
> 15V. A
1 33
.
IN
and
IN
=