LTC3731HG Linear Technology, LTC3731HG Datasheet - Page 8

• Manufacturer Part Number: LTC3731HG
• Description: IC REG SW SYNC 3PH STPDWN 36SSOP
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck)r

Specifications of LTC3731HG

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.6 ~ 6 V
• Frequency - Switching: 225kHz ~ 680kHz
• Voltage - Input: 4 ~ 36 V
• Operating Temperature: -40°C ~ 140°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Not Compliant

LTC3731H
BG1 to BG3: High Current Gate Drives for Bottom N-Channel
MOSFETs. Voltage swing at these pins is from ground to V
BOOST1 to BOOST3: Positive Supply Pins to the Topside
Floating Drivers. Bootstrapped capacitors, charged with
external Schottky diodes and a boost voltage source, are
connected between the BOOST and SW pins. Voltage swing
at the BOOST pins is from boost source voltage (typically
V
external MOSFET supply rail).
CLKOUT: Output clock signal available to synchronize other
controller ICs for additional MOSFET stages/phases.
EAIN: This is the input to the error amplifier that compares the
feedback voltage to the internal 0.6V reference voltage.
FCB: Forced Continuous Control Input. The voltage applied to
this pin sets the operating mode of the controller. The forced
continuous current mode is active when the applied voltage is
less than 0.6V. Burst Mode operation will be active when the
pin is allowed to float and a Stage Shedding mode will be active
if the pin is tied to the V
this pin prior to the application of voltage on the V
PGOOD: This open-drain output is pulled low when the output
voltage has been outside the PGOOD tolerance window for the
V
I
sation Point. All three current comparator’s thresholds in-
crease with this control voltage.
PGND: Driver Power Ground. This pin connects directly to the
sources of the bottom N-channel external MOSFETs and the
(–) terminals of C
PHASMD: This pin determines the phase shift between the first
controller’s rising TG signal and the rising edge of the CLKOUT
signal. Logic 0 yields 30 degrees and Logic 1 yields 60 degrees.
PLLIN: Synchronization Input to Phase Detector. This pin is
internally terminated to SGND with 50kΩ. The phase-locked
loop will force the rising top gate signal of controller 1 to be
synchronized with the rising edge of the PLLIN signal.
PI FU CTIO S
8
TH
CC
PGDLY
: Error Amplifier Output and Switching Regulator Compen-
U
) to this boost source voltage + V
delay of approximately 100µs.
U
IN
.
U
CC
pin. (Do not apply voltage directly to
IN
(where V
CC
IN
pin.)
is the
CC
.
PLLFLTR: The phase-locked loop’s lowpass filter is tied to this
pin. Alternatively, this pin can be driven with an AC or DC
voltage source to vary the frequency of the internal oscillator.
(Do not apply voltage directly to this pin prior to the application
of voltage on the V
RUN/SS: Combination of Soft-Start, Run Control Input and
Short-Circuit Detection Timer. A capacitor to ground at this
pin sets the ramp time to full current output as well as the time
delay prior to an output voltage short-circuit shutdown. A
minimum value of 0.01µF is recommended on this pin.
SENSE1
The Inputs to Each Differential Current Comparator. The I
voltage and built-in offsets between SENSE
in conjunction with R
SGND: Signal Ground. This pin must be routed separately
under the IC to the PGND pin and then to the main ground
plane.
SW1 to SW3: Switch Node Connections to Inductors. Voltage
swing at these pins is from a Schottky diode (external) voltage
drop below ground to V
supply rail).
TG1 to TG3: High Current Gate Drives for Top N-channel
MOSFETs. These are the outputs of floating drivers with a
voltage swing equal to the boost voltage source superimposed
on the switch node voltage SW.
UVADJ: Input to the Undervoltage Shutdown Comparator.
When the applied input voltage is less than 1.2V, this compara-
tor turns off the output MOSFET driver stages and discharges
the RUN/SS capacitor.
V
controller circuit power as well as the high power pulses
supplied to drive the external MOSFET gates, this pin needs to
be very carefully and closely decoupled to the IC’s PGND pin.
VDR: Supplies power to the bottom gate drivers only. This pin
needs to be very carefully and closely decoupled to the IC’s
PGND pin.
CC
: Main Supply Pin. Because this pin supplies both the
+
, SENSE2
+
CC
, SENSE3
SENSE
pin.)
IN
(where V
, set the current trip threshold level.
+
, SENSE1
IN
is the external MOSFET
–
, SENSE2
–
and SENSE
–
, SENSE3
+
TH
3731hfa
pins,
pin
–
: