IP2021CTRPBF International Rectifier, IP2021CTRPBF Datasheet - Page 12

• Manufacturer Part Number: IP2021CTRPBF
• Description: IC PWR BLOCK SYN 2PH DUAL LGA
• Manufacturer: International Rectifier
• Series: iPOWIR™r
• Type: Step-Down (Buck)r

Specifications of IP2021CTRPBF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.8 ~ 5 V
• Current - Output: 30A
• Frequency - Switching: 300kHz ~ 1MHz
• Voltage - Input: 8 ~ 14 V
• Operating Temperature: -10°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 12-LLGA
• Power - Output: 11.2W
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCB Layout Guidelines
The following guidelines are recommended to reduce the parasitic values and optimize overall
performance.
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L1
V
•
•
•
•
•
•
SW
Top Component Layer
All pads on the iP2005C footprint design need to be Solder-mask defined (see Figure 13).
Also refer to International Rectifier application notes AN1028 and AN1029 for further footprint
design guidance.
Place as many vias around the Power pads (V
thermal performance.
A minimum of six 10µF, X5R, 16V ceramic capacitors per iP2005C are needed for greater
than 30A operation at 1MHz switching frequency. This will result in the lowest loss due to
input capacitor ESR.
Placement of the ceramic input capacitors is critical to optimize switching performance. In
cases where there is a heatsink on the case of iP2005C, place all six ceramic capacitors right
underneath the iP2005C footprint (see Figure Bottom Component Layer). In cases where
there is no heatsink, C1 and C6 on the bottom layer may be moved to the C1x and C6x
locations (respectively) on the top component layer (see Figure Top Component Layer). In
both cases, C2 – C5 need to be placed right underneath the iP2005C PCB footprint.
Dedicate at least two layers to PGND.
Duplicate the Power Nodes on multiple layers (refer to AN1029).
Figure 14 Top & Bottom Component and Via Placement (Topside, Transparent view down)
U1
P
C1x
V
GND
IN
P
V
V
GND
1
2
3
SW
IN
P
C6x
V
GND
IN
ENABLE
PWM
N/C
N/C
V
04/09/2009
6
5
4
8
7
DD
IN
, V
Bottom Component Layer
SW
, and P
GND
P
C3
V
GND
) for both electrical and optimal
IN
iP2005CPbF
P
V
C4
GND
IN
P
C2
V
GND
IN
P
V
GND
PD-60360
IN
C5
P
C1
V
GND
IN
P
C6
V
GND
IN
12