DS2401P+T&R Maxim Integrated Products, DS2401P+T&R Datasheet - Page 10

• Manufacturer Part Number: DS2401P+T&R
• Description: IC SILICON SERIAL NUMBER 6-TSOC
• Manufacturer: Maxim Integrated Products

Specifications of DS2401P+T&R

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 6-TSOC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS2401P+T&R

NOTES:
1) All voltages are referenced to ground.
2) V
3) Input load is to ground.
4) An additional reset or communication sequence cannot begin until the reset high time has expired.
5) Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
6) V
7) 30 nanocoulombs per 72 time slots @ 5.0V.
8) At V
9) Capacitance on the I/O pin could be 800pF when power is first applied. If a 5k Ω resistor is used to
10) The reset low time (t
11) The optimal sampling point for the master is as close as possible to the end time of the t
12) The duration of the low pulse sent by the master should be a minimum of 1μs with a maximum value
guaranteed to be valid within 1 μ s of this falling edge and will remain valid for 14 μ s minimum (15 μ s
total from falling edge on 1-Wire bus).
pullup the I/O line to V
normal communications.
otherwise it could mask or conceal interrupt pulses if this device is used in parallel with a DS2404 or
DS1994.
without exceeding t
the pullup resistor to recover to a high level. For a Read-Zero Time slot, it ensures that a read will
occur before the fastest 1-Wire device(s) releases the line.
as short as possible to allow time for the pullup resistor to recover the line to a high level before the 1-
Wire device samples in the case of a Write-One Time or before the master samples in the case of a
Read-One Time.
PUP
IH
is a function of the external pullup resistor and the V
CC
= external pullup voltage.
= 5.0V with a 5k Ω pullup to V
RDV
RSTL
. For the case of a Read-One Time slot, this maximizes the amount of time for
CC
) should be restricted to a maximum of 960 μ s, to allow interrupt signaling,
, 5 μ s after power has been applied the parasite capacitance will not affect
CC
and a maximum time slot of 120 μ s.
10 of 10
CC
supply.
RDV
period