STV0974E/TR STMicroelectronics, STV0974E/TR Datasheet
STV0974E/TR
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STV0974E/TR
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STV0974E/TR Summary of contents
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... CMOS (VS6552) Frame rate (frame/ Power supply 1.8 +/- 0.1 V Power requirements 110 mW active < 30 µW standby Package dimensions 1.2 mm Temperature range [ -25; +70 ] °C Ordering Information Ordering code STV0974/TR TFBGA SnPb balls STV0974E/TR TFBGA AFOP lead-free balls STV0974 Package Rev. 3 1/69 ...
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STV0974 Contents Chapter 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Chapter 8 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The STV0974 is a mobile imaging digital signal processor which, when used with VS6552 CMOS color VGA image sensor from STMicroelectronics, performs all the required data processing to deliver good quality Viewfinder, still and live color images. The STV0974 performs high quality color processing on images, achieving JPEG compression if requested and transfers them to a baseband through one of the available interfaces ...
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Functional block diagram 2 Functional block diagram Figure 1: Functional block diagram POR RST management PCLKP PCLKN PDATAP PDATAN MSCL MSDA STV0974 5/61 CLK PDN Clock & Power RAM - ROM Microprocessor Internal bus VC VisionLink serial receiver VP I2C ...
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STV0974 3 Signal description Table 1: STV0974 signal description Pin name Power supplies VDD VCORE VDDPOR VSS Sensor interface PDATAP, PDATAN PCLKP, PCLKN MSDA MSCL Host interface POR RST CLK PDN DIO[0:11]DIO[13] DIO[12] SDA SCL Test interface (ST internal use) ...
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Functional description 4 Functional description 4.1 Overview The processor includes a chain of dedicated video data processing blocks controlled by a microprocessor. The processing blocks perform the main video pipe processing while the microprocessor manages the interactions between the sensor, ...
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STV0974 4.1.2 Control Register map The STV0974 is controlled via a register map that is maintained by the STV0974 microprocessor. Each register in the map has an address and contains either read or read/write data. The read only registers detail ...
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Functional description 4.2 Sensor interface 4.2.1 Features Low electromagnetic interference (EMI) interface with CMOS image sensors ● High speed serial receiver, with data and clock inputs ● 120 Mbit/s operation using very low voltage differential signaling (vLVDS) ● ...
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STV0974 4.3 Video processing unit 4.3.1 Features Low-power dedicated hardware video processing unit, pipeline operation up to VGA resolution ● Image sensor correction stage including pixel defect correction and fixed pattern noise (FPN) ● cancellation Color interpolation stage ...
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Functional description Color matrix Each pixel (RGB vector) is multiplied by a color matrix to adjust color balance. Viewfinder and live settings are independent to allow for optimization of both LCD display and capture for later viewing (i. ...
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STV0974 Table 4: Output video formats Name UYVY RGB565 RGB444 ...
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Functional description 4.4 Video compression (VC) Real time video compression permits a frame rate of 30 frame/s in any mode at VGA. The JPEG compression engine is a standard baseline sequential JPEG encoder The compression ratio can be modified by ...
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STV0974 4.4.1 Raster to block converter This block transforms the raster scan ordered data into block based ordered data. This data ordering is compliant with ISO DIS 10918-1 Annex A - Section A.2. Figure 4: Data sequence at Raster to ...
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Functional description The MCU sequence order is top left to top right and top to bottom. Figure 6 shows the MCU structure made of 4 blocks: 2 blocks of 8x8 Y component, 1 block of 8x8 U component and one ...
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STV0974 4.4.2 Discrete Cosine Transform This block performs a Discrete Cosine Transform on the incoming data stream compliant with ISO DIS 10918-1 Annex A - Section A.3. The block processes each 8x8 input block to transform them into ...
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Functional description 4.4.4 Quantization block This block applies a uniform quantizer on all DCT coefficients, in ZigZag sequence compliant with ISO DIS 10918-1 Annex A - Section A.3.4. The quantizer step size for each DCT coefficient S from ...
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STV0974 4.4.5 Entropy coder This block performs the following functions: insertion of JPEG Markers ● runlength encoding ● Huffman encoding ● 4.4.5.1 JPEG markers These markers are compliant with ISO DIS 10918-1 Annex B. The output JPEG file includes markers ...
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Functional description The Huffman table used are described in ISO DIS 10918-1 Annex A - Section K.3. Figure 11: Encoding of AC coefficient Block Y1 data values In the above example, the first ...
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STV0974 4.5 Microprocessor interface 4.5.1 Features 8-bit microprocessor interface, asynchronous read/write, one address bit ● Indirect access to image sensor and coprocessor control registers ● Direct access to image data (JPEG compressed or uncompressed) ● On-chip 2048 byte image FIFO ...
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Functional description 4.5.3 Direct registers Access to the microprocessor interface direct registers is controlled by the state of CSN, RDN, Table 8 WRN and RS ( Table 8: Microprocessor Interface Direct Registers CSN RDN WRN ...
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STV0974 Status Register (SR) The status register is an 8-bit read-only direct register holding all pending requests from the camera subsystem. Table 10: Status Register Bits Name Type 7 IRQ EOF - 4 SOF RO ...
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Functional description Data Write Register (DW) The data write register contains the byte to transfer to a camera register. DW can be written only when SR bit RDY is set. Table 11: Data write register Bits Name Type [7:0] DW ...
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STV0974 FIFO Register (FIFO) FIFO is a read-only register. When read, FIFO returns the least recent byte from the image data FIFO, decrements the byte count and releases the FIFO interrupt if the count is lower than the threshold. Reading ...
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Functional description Interrupt Mask Register (IMASK) Table 16: Interrupt Mask Register Bits Name Type [7: [5:0] IMASK RW Interrupt Clear Register (ICLR) Table 17: Interrupt Clear Register Bits Name Type [7:6] - [5:2] ICLR WO [1:0] - FIFO ...
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STV0974 FIFO Count Register (FCNT) FCNT is a read-only 16-bit register, returning the current number of bytes available in the FIFO. Table 20: FIFO Count Register Bits Name Type [15:0] FCNT RO 4.5.5 Image transfer operation Interrupt controlled transfer The ...
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Functional description 4 DRQ is released after the first byte is read. 5 After the last byte of the burst is read, the transfer terminates on step 6 if the FIFO is empty and the frame end is reached. Otherwise, ...
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STV0974 4.6 Video output interface 4.6.1 Video synchronization The STV0974 supports two modes of data stream synchronization. Either the data stream can be synchronized by separate HSYNC and VSYNC signal (see codes in the data stream (see 4.6.2 Synchronization codes ...
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Functional description 4.6.3 HSYNC and VSYNC video synchronization HSYNC and VSYNC synchronization timing is shown in the Figure 15: Horizontal and vertical synchronization HSYNC VSYNC V=0 V=1 4.6.4 Data timing The YUV timing and the 3 RGB timings are also ...
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STV0974 4.6.5 JPEG data on 8-bit parallel with qualification clock This interface outputs JPEG on parallel 8-bit IOs. Different synchronization can be provided, as Figure 17 described in There are no defined lines in a JPEG data stream. The whole ...
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Functional description 4.7 Power management unit The STV0974 is reset via the internal PowerOnReset cell (POR) or via an external control reset line. The device reset is controlled by the RST pin. The POR cell generates an output signal on ...
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... The “timing constraints” mentioned above correspond to the minimum delay needed between signals, in order to follow a correct power up sequence and insure an adequate initialization phase. Referring to the application schematics ( POR pin (internal supply) to RST pin (Reset Reset Boot Min Section 8 ), STMicroelectronics recommends to connect Functional description Sleep Max. Unit ms µs clk cycles ms µs 32/61 ...
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Functional description 4.8 Clock input This block generates all the necessary internal clocks from an input range defined in input clock pad accepts MHz signals. Table 22: System input clock frequency range Min. (MHz) a. Standard supported ...
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STV0974 4.9 Camera control unit 4.9.1 Features User mode transition ● register map including high-level registers and low-level registers dedicated to scaler ● control 4.9.2 Description Figure 21: State machine user mode transitions VDD Power down Sleep ...
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Functional description Still Mode This mode is used to take still pictures. Still picture parameters can be set for both image size and data format. the first image output has a guaranteed exposure and color balance. the number of frames ...
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STV0974 Idle to viewfinder / live The sensor field and line lengths are set according to user-defined frame rate and data output format. The STV0974 processes all sensor data on the fly. Exposure and white balance controls are computed at ...
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Functional description Viewfinder to live/ Live to viewfinder The sensor field and frame lengths are set according to the user defined Live/Capture frame rate and data output format. The latency of this transition is minimal. See Figure 25 Figure 25: ...
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STV0974 Once the image is sent, the STV0974 automatically returns to Idle. See Figure 27: Viewfinder to capture timing SCL/SDA capture ViewFinder 974 mode STV0974 output data MSCL/MSDA Sensor mode VisionLink data Note the system exposure and white ...
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Functional description 4.9.3 I²C register map Register interpreter The STV0974 I²C address is 0x08. The addressing space is defined in Table 23: Fields of address map Index Bit [12-8] [7-0] The customer accessible register map is divided ...
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STV0974 There are restrictions related to the states at which registers can be accessed. state coding used in the register description. Table 25: Register state coding State code Register contents represent different data types ...
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Functional description 4.9.3.1 High-level interface Register group 0 Table 27: System and status [register group 0] Name Index Sensor ID Code 0xA000 MSB Sensor ID Code 0xA001 LSB Firmware Rom 0xA002 Version External Clock 0xA004 a Frequency MSB External Clock ...
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STV0974 Table 27: System and status [register group 0] Name Index Input / Output 0xA00A Protocol Control a. See Clock input section, for standard external clock frequencies supported. b. The product limitation in derating mode Half Speed ...
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Functional description Register group 1 Table 28: Image characteristics [Register group 1] Name Index Still and Live 0xA100 Sensor Frame a Rate Still and Live 0xA101 Output Image Size Still and Live 0xA102 Output Image Format Still Multi-frames 0xA103 Transfer ...
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STV0974 Table 28: Image characteristics [Register group 1] Name Index Viewfinder Image 0xC107 Format a. The corresponding frame rates are considered as targets. If the target cannot be achieved due to derated sensor clock or output format versus output protocol, ...
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Functional description Register group 2 Table 29: Image control [register group 2] Name Index Antivignetting 0xA200 Correction DEFCOR control 0xA201 NORA control 0xA202 Mirror 0xA203 Sharpness Gain 0xA204 Sharpness 0xA205 Enable JPEG Control 0xA206 45/61 State Data Format R/W code ...
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STV0974 Register group 3 Table 30: Color management [register group 3] Name Index Still / live Gamma 0xA300 Standard Gain Still / live Gamma 0xA301 S-Curve gain Still / live Gamma 0xA302 Misc. Viewfinder 0xA303 Gamma Standard Gain Viewfinder 0xA304 ...
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Functional description Register group 4 Table 31: Exposure management [Register group 4] Name Index AC Frequency 0xA400 Exposure 0xA401 weighting Exposure 0xA402 compensation Register Group 5 Table 32: White balance management [register group 5] Name Index White Balance 0xA500 Mode ...
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STV0974 Register Group 6 Table 33: Flash mode management [register group 6] Name Index Torch polarity 0x8A43 Torch control 0x8A44 Flash pulse 0x8A45 polarity Flash pulse length 0x88D4 Note: Access to the bits mentioned here above is done through a ...
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Functional description 4.9.3.2 Low-level interface Scaler low-level control These registers are active only if either “ Size ” registers are set to “custom” size. Table 34: Scaler low-level control Name Index Source centre X- 0x8060 position MSB Source centre X- ...
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STV0974 Table 34: Scaler low-level control Name Index Still / Live Scaling 0x806D factor Note: If the scaling factor it too high and the cropped image size is bigger than the full source image, the scaling factor is automatically set ...
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Functional description Figure 29: MMS crop zoom example 4.9.3.3 Status error codes A read from the Status Register (0xA009) yields status error codes as described in the table below. The Status Register contents are reset to 0x00 ...
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STV0974 4.9.3.4 Firmware patching The STV0974 has some firmware patching capabilities addressable through I microprocessor interfaces through control registers firmware patch code downloads different patches can be downloaded within a limit of 512 bytes of RAM. Name ...
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Electrical characteristics 5 Electrical characteristics 5.1 Absolute maximum ratings Symbol V Supply voltage DD (including VCORE & VDDPOR) Voltage on any signal pin I Supply current DD Current on any signal pin T Storage temperature STO T Lead temperature (soldering, ...
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STV0974 5.4 DC electrical characteristics Over operating conditions unless otherwise specified. Symbol Parameter V Input low voltage IL V Input high voltage IH V Output low voltage OL V Output high voltage OH I Input leakage current IL Input pins ...
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Electrical characteristics 5.5 AC electrical characteristics 5.5.1 CLK Table 38: CLK electrical characteristics ( Symbol V DC coupled square wave voltage CDC f Clock frequency input CLK Figure 30: CLK electrical characteristics V CDC 2 5.5 slave timing ...
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STV0974 2 Figure 31 slave timing Stop Start SDA t BUF SCL t HD.STA Note the same timing when the host is driving. 2 5.5 master timing 2 Table 40: I ...
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Electrical characteristics 2 Figure 32 master timing Stop Start SDA t BUF SCL t HD.STA the same timing when the host is driving. 57/ LOW ...
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STV0974 5.5.4 Video output timing Table 41: Video output timing ( Symbol t Data and synchro setup time DS t Data and synchro hold time DH t Clock pulse width high CKH t Clock period CKP t Clock rise time ...
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Electrical characteristics Figure 34: Read cycle timing (WRN high) Data[7:0] Figure 35: Write cycle timing (RDN high) Data[0:7] 5.5.6 VisionLink serial receiver timing Table 43: VisionLink serial receiver input timing ( Symbol t Data setup time DS t Data hold ...
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STV0974 Figure 36: VisionLink basic input timing PCLK PDATA Table 44: Receiver VisionLink / SubLVDS electrical characteristics Symbol V Input common mode voltage range I V Input differential threshold IDTH (Va -Vaz) t Power-up/-down time PWRUP/ PWRDN ...
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Package mechanical data 6 Package mechanical data 6.1 Pin assignment Figure 37: STV0974 pin assignment 61/ VSS DIO2 DIO1 DIO0 RST POR VDD NC ...
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STV0974 6.2 Package dimensions Table 45: TFBGA 6x6x1.20 56 2R10 0.50 - Package dimensions Reference ddd d .eee e .fff a. Max mounted height is 1.20mm. Based on a 0.27mm ...
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Package mechanical data Figure 38: TFBGA 56 6x6x1.2 2R10 0.5 seating plane C 63/ corner index ...
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STV0974 7 PCB layout guide lines for the STV0974 and VS6552 Normal good PCB design practice should be observed for the layout of the STV0974. Power and ground planes should be used to supply power to STV0974. The high speed ...
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Application schematics 8 Application schematics Figure 39: Mobile camera application, 8-bit parallel video interface, V 65/61 STV0974 = 2.8V with low level shifter I/O ...
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STV0974 Figure 40: Mobile camera application, microprocessor interface, V Application schematics = 1.8V, no low level shifter I/O 66/61 ...
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Evaluation kit and demonstration boards 9 Evaluation kit and demonstration boards A number of support kits are available. The evaluation kit is recommended for evaluation and system integration open system and electrical connections can be made ...
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STV0974 Revision history Revision Date 0.1 December 2003 0.2 January 2004 1 April 2004 1 June 2004 2 28 Oct 2004 3 23 Nov 2004 References [1] ITU-R Rec.BT.656-4. Interfaces for digital component video signals in 525-line and 625-line television ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...