ADUM5242ARZ Analog Devices Inc, ADUM5242ARZ Datasheet - Page 4

• Manufacturer Part Number: ADUM5242ARZ
• Description: IC ISOLATOR 2CH W/CONV 8-SOIC
• Manufacturer: Analog Devices Inc
• Series: IsoPower®, iCoupler®r

Specifications of ADUM5242ARZ

• Propagation Delay: 70ns
• Inputs - Side 1/side 2: 0/2
• Number Of Channels: 2
• Isolation Rating: 2500Vrms
• Voltage - Supply: 3.35V, 4.1V, 5V
• Data Rate: 1Mbps
• Output Type: Logic
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature: -40°C ~ 105°C
• No. Of Channels: 2
• Supply Current: 140mA
• Supply Voltage Range: 2.7V To 4V, 4.5V To 5.5V
• Digital Ic Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To
• Package: 8SOIC N
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 105C
• Package Type: SOIC N
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuM5240/ADuM5241/ADuM5242
Parameter
AC SPECIFICATIONS
1
2
3
4
5
6
7
8
9
Peak noise occurs at frequency corresponding to the refresh frequency (see the PCB Layout section).
I
I
Enable/disable threshold is the V
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion and V
t
measured from the 50% level of the rising edge of the V
t
load within the recommended operating conditions.
Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads.
DD (DISABLE)
ISO (DISABLE)
PHL
PSK
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching,
Channel-to-Channel Matching,
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient
Common-Mode Transient
Refresh Frequency
Switching Frequency
propagation delay is measured from the 50% level of the falling edge of the V
is the magnitude of the worst-case difference in t
Codirectional Channels
Opposing-Directional Channels
Immunity at Logic High Output
Immunity at Logic Low Output
supply current values are specified with no load present on the digital outputs.
supply current values are specified with no load present on the digital outputs and power sourced by an external supply.
7
6
5
8
PLH
9
DD
− t
voltage at which the internal dc-to-dc converter is enabled/disabled.
PHL
|
8
9
PHL
Symbol
PW
t
PWD
t
t
t
t
|CM
|CM
f
f
r
OSC
PHL
PSK
PSKCD
PSKCD
R
/t
and/or t
Ix
, t
F
signal to the 50% level of the rising edge of the V
H
L
|
|
PLH
PLH
that is measured between units at the same operating temperature, supply voltages, and output
Min
1
25
25
25
Rev. A | Page 4 of 16
Ix
signal to the 50% level of the falling edge of the V
Typ
2.5
35
35
1.0
300
ISO
supply voltage is guaranteed.
Max
100
70
3
45
3
15
Ox
signal.
Unit
ns
Mbps
ns
ns
ns
ns
ns
ns
kV/μs
kV/μs
MHz
MHz
Test Conditions
C
C
C
C
C
C
C
C
V
transient magnitude = 800 V
V
transient magnitude = 800 V
Ix
Ix
L
L
L
L
L
L
L
L
Ox
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= V
= 0 V, V = 1000 V,
signal. t
DD
, V
PLH
ISO
, V
propagation delay is
CM
= 1000 V,