SI8452AA-B-IS1 Silicon Laboratories Inc, SI8452AA-B-IS1 Datasheet
SI8452AA-B-IS1
Specifications of SI8452AA-B-IS1
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SI8452AA-B-IS1 Summary of contents
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... IEC 60950-1, 61010-1 (reinforced insulation ) Description Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages when compared to legacy isolation technologies. The operating parameters of these products remain stable across wide temperature ranges throughout their service life ...
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Si8450/51/52/55 2 Rev. 1.3 ...
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T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si8450/51/52/55 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Operating Temperature* Supply Voltage *Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage. Table 2. Absolute Maximum Ratings Parameter ...
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Table 3. Electrical Characteristics ( V±10 V±10%, T DD1 DD2 A Parameter Symbol High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current 1 Output Impedance ...
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Si8450/51/52/55 Table 3. Electrical Characteristics (Continued V±10 V±10%, T DD1 DD2 A Parameter Symbol 10 Mbps Supply Current (All inputs = 5 MHz square wave all outputs) Si8450Bx, Si8455Bx ...
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Table 3. Electrical Characteristics (Continued V±10 V±10%, T DD1 DD2 A Parameter Symbol Si845xBx Maximum Data Rate Minimum Pulse Width Propagation Delay t PHL Pulse Width Distortion | PLH PHL 2 ...
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Si8450/51/52/55 ENABLE OUTPUTS 1.4 V Typical Input t PLH 90% 1.4 V 10% Typical Output 8 t en1 Figure 1. ENABLE Timing Diagram t PHL 90% 10 Figure 2. Propagation Delay Timing Rev. 1.3 t en2 ...
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Table 4. Electrical Characteristics (V = 3.3 V±10 3.3 V±10%, T DD1 DD2 Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current 1 Output Impedance Enable Input ...
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Si8450/51/52/55 Table 4. Electrical Characteristics (Continued 3.3 V±10 3.3 V±10%, T DD1 DD2 Parameter 10 Mbps Supply Current (All inputs = 5 MHz square wave all outputs) Si8450Bx, Si8455Bx V DD1 ...
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Table 4. Electrical Characteristics (Continued 3.3 V±10 3.3 V±10%, T DD1 DD2 Parameter Si845xBx Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion | PLH PHL 2 Propagation Delay Skew Channel-Channel ...
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Si8450/51/52/55 Table 5. Electrical Characteristics ( –40 to 125 ºC; applies to narrow and wide-body SOIC packages) DD1 DD2 A Parameter High Level Input Voltage Low Level Input Voltage High Level ...
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Table 5. Electrical Characteristics ( –40 to 125 ºC; applies to narrow and wide-body SOIC packages) DD1 DD2 A Parameter 10 Mbps Supply Current (All inputs = 5 MHz square wave, ...
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Si8450/51/52/55 Table 5. Electrical Characteristics ( –40 to 125 ºC; applies to narrow and wide-body SOIC packages) DD1 DD2 A Parameter Si845xBx Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse ...
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Table 6. Regulatory Information* CSA The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. 61010- 600 V reinforced insulation working voltage 600 V RMS 60950- 130 V ...
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Si8450/51/52/55 Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings Parameter Basic Isolation Group Installation Classification Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB* Parameter Maximum Working Insulation Voltage Input to Output Test Voltage Transient Overvoltage Pollution Degree (DIN VDE ...
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Table 11. Thermal Characteristics Parameter Symbol IC Junction-to-Air Thermal JA Resistance 500 400 300 200 100 0 Figure 3. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 500 400 300 ...
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Si8450/51/52/55 2. Functional Description 2.1. Theory of Operation The operation of an Si845x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path ...
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Eye Diagram Figure 7 illustrates an eye-diagram taken on an Si8450. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8450 ...
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Si8450/51/52/55 2.3. Device Operation Device behavior during start-up, normal operation, and shutdown is shown in Table 12. Table 13 provides an overview of the output states when the Enable pins are active. Table 12. Si845x Logic Operation Table V EN ...
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P/N 1,2 1,2 EN1 EN2 Si8450 — H Outputs B1, B2, B3, B4, B5 are enabled and follow input state. — L Outputs B1, B2, B3, B4, B5 are disabled and Logic Low or in high impedance state. Si8451 H ...
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Si8450/51/52/55 2.4. Layout Recommendations To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 V separated from the safety extra-low voltage circuits (SELV is a circuit with <30 V (creepage/clearance component, such as ...
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Typical Performance Characteristics The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to Tables 3, 4, and 5 for actual specification limits ...
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Si8450/51/52/55 10 Falling Edge -40 - Temperature (Degrees C) Figure 14. Propagation Delay vs. Temperature 24 Rising Edge 80 100 120 Rev. 1.3 ...
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Figure 15. Si84xx Time-Dependent Dielectric Breakdown Rev. 1.3 Si8450/51/52/55 25 ...
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... Power Supply Bypass Capacitors (Revision A and Revision B) When using the ISOpro isolators with power supplies > 4.5 V, sufficient VDD bypass capacitors must be present on both the VDD1 and VDD2 pins to ensure the VDD rise time is less than 0.5 V/µs (which is > 9 µs for a > 4.5 V supply). Although rise time is power supply dependent, > ...
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Pin Descriptions (Si8450/51/52 DD1 DD2 XMITR RCVR XMITR RCVR XMITR RCVR XMITR RCVR i RF ...
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Si8450/51/52/55 5. Pin Descriptions (Si8455) Name SOIC-16 Pin DD1 GND1 GND1 8 GND2 GND2 15 V ...
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... Ordering Guide Revision B devices are recommended for all new designs. Table 15. Ordering Guide for Valid OPNs Ordering Part Number of Number (OPN) Inputs VDD1 Side 2 Revision B Devices Si8450AA-B-IS1 5 Si8450BA-B-IS1 5 Si8451AA-B-IS1 4 Si8451BA-B-IS1 4 Si8452AA-B-IS1 3 Si8452BA-B-IS1 3 Si8455BA-B-IS1 5 Si8450AB-B-IS1 5 Si8450BB-B-IS1 5 Si8451AB-B-IS1 4 Si8451BB-B-IS1 4 Si8452AB-B-IS1 3 Si8452BB-B-IS1 3 Si8455BB-B-IS1 5 Notes: 1. All packages are RoHS-compliant. Moisture sensitivity level is MSL2A with peak reflow temperature of 260 ° ...
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... Si8450/51/52/55 Table 15. Ordering Guide for Valid OPNs Ordering Part Number of Number (OPN) Inputs VDD1 Side 2 Revision A Devices Si8450AA-A-IS1 5 Si8450BA-A-IS1 5 Si8451AA-A-IS1 4 Si8451BA-A-IS1 4 Si8452AA-A-IS1 3 Si8452BA-A-IS1 3 Si8455BA-A-IS1 5 Si8450AB-A-IS1 5 Si8450BB-A-IS1 5 Si8451AB-A-IS1 4 Si8451BB-A-IS1 4 Si8452AB-A-IS1 3 Si8452BB-A-IS1 3 Si8455BB-A-IS1 5 Notes: 1. All packages are RoHS-compliant. Moisture sensitivity level is MSL2A with peak reflow temperature of 260 °C according to the JEDEC industry standard classifications and peak solder temperature ...
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Package Outline: 16-Pin Wide Body SOIC Figure 16 illustrates the package details for the Si845x Digital Isolator. Table 16 lists the values for the dimensions shown in the illustration. Table 16. Package Diagram Dimensions Figure 16. 16-Pin Wide Body ...
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Si8450/51/52/55 8. Land Pattern: 16-Pin Wide-Body SOIC Figure 17 illustrates the recommended land pattern details for the Si845x in a 16-pin wide-body SOIC. Table 17 lists the values for the dimensions shown in the illustration. Table 17. 16-Pin Wide Body ...
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Package Outline: 16-Pin Narrow Body SOIC Figure 18 illustrates the package details for the Si845x in a 16-pin narrow-body SOIC (SO-16). Table 18 lists the values for the dimensions shown in the illustration. Figure 18. 16-pin Small Outline Integrated ...
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Si8450/51/52/55 Table 18. Package Diagram Dimensions (Continued) h θ aaa bbb ccc ddd Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid ...
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Land Pattern: 16-Pin Narrow Body SOIC Figure 19 illustrates the recommended land pattern details for the Si845x in a 16-pin narrow-body SOIC. Table 19 lists the values for the dimensions shown in the illustration. Figure 19. 16-Pin Narrow Body ...
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Si8450/51/52/55 11. Top Marking: 16-Pin Wide Body SOIC Figure 20. Si8450/51/52/55 Top Marking Base Part Number Line 1 Marking: Ordering Options (See Ordering Guide for more information Year Line 2 Marking Workweek TTTTTT = Mfg Code ...
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Top Marking: 16-Pin Narrow Body SOIC Figure 21. 16-Pin Narrow Body SOIC Top Marking Table 21. 16-Pin Narrow Body SOIC Top Marking Table Base Part Number Ordering Options Line 1 Marking: (See Ordering Guide for more information). Circle = ...
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Si8450/51/52/ OCUMENT HANGE IST Revision 0.1 to Revision 0.2 Updated all specs to reflect latest silicon. Added "3. Errata and Design Migration Guidelines" on page 26. Added "12. Top Marking: 16-Pin Narrow Body SOIC" ...
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N : OTES Si8450/51/52/55 Rev. 1.3 39 ...
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