HCPL-J314-300E Avago Technologies US Inc., HCPL-J314-300E Datasheet - Page 15

• Manufacturer Part Number: HCPL-J314-300E
• Description: OPTOCOUPLER 1CH 0.6A 8-SMD GW
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-J314-300E

• Package / Case: 8-SMD Gull Wing
• Voltage - Isolation: 3750Vrms
• Number Of Channels: 1, Unidirectional
• Current - Output / Channel: 600mA
• Propagation Delay High - Low @ If: 300ns @ 8mA
• Current - Dc Forward (if): 25mA
• Input Type: DC
• Output Type: Push-Pull, Totem-Pole
• Mounting Type: Surface Mount, Gull Wing
• Isolation Voltage: 3750 Vrms
• Maximum Fall Time: 50 ns
• Maximum Forward Diode Current: 25 mA
• Maximum Rise Time: 50 ns
• Minimum Forward Diode Voltage: 1.2 V
• Output Device: Integrated Photo IC
• Configuration: 1 Channel
• Maximum Forward Diode Voltage: 1.8 V
• Maximum Reverse Diode Voltage: 3 V
• Maximum Power Dissipation: 260 mW
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Number Of Elements: 1
• Forward Voltage: 1.8V
• Forward Current: 25mA
• Package Type: PDIP SMD
• Operating Temp Range: -40C to 100C
• Power Dissipation: 260mW
• Propagation Delay Time: 700ns
• Pin Count: 8
• Mounting: Surface Mount
• Reverse Breakdown Voltage: 3V
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

CMR with the LED On (CMR
A high CMR LED drive circuit must keep the LED on
during common mode transients. This is achieved by
overdriving the LED current beyond the input threshold
so that it is not pulled below the threshold during a
transient. A minimum LED current of 8 mA provides
adequate margin over the maximum IFigure 26. Minimum
LED Skew for Zero Dead Time.Figure 27. Waveforms for
Dead Time. of 5 mA to achieve 10 kV/µs CMR.
CMR with the LED Off (CMR
A high CMR LED drive circuit must keep the LED off (V
≤ V
during a -dV
flowing through C
VSAT of the logic gate. As long as the low state voltage
developed across the logic gate is less than V
LED will remain off and no common mode failure will
occur.
The open collector drive circuit, shown in Figure 24, can
not keep the LED off during a +dV
all the current flowing through C
by the LED, and it is not recommended for applications
requiring ultra high CMR1 performance. The alternative
drive circuit which like the recommended application
circuit (Figure 19), does achieve ultra high CMR perfor-
mance by shunting the LED in the off state.
F(OFF)
) during common mode transients. For example,
CM
/dt transient in Figure 23, the current
LEDP
also flows through the RSAT and
H
L
)
)
LEDN
CM
/dt transient, since
must be supplied
F(OFF)
the
F
IPM Dead Time and Propagation Delay Specifications
The HCPL-J314 includes a Propagation Delay Dif-
ference (PDD) specification intended to help
designers minimize “dead time” in their power
inverter designs. Dead time is the time high and
low side power transistors are off. Any overlap
in Ql and Q2 conduction will result in large currents
flowing through the power devices from the high-
voltage to the low-voltage motor rails. To minimize dead
time in a given design, the turn on of LED2 should be
delayed (relative to the turn off of LED1) so that under
worst-case conditions, transistor Q1 has just turned off
when transistor Q2 turns on, as shown in Figure 26. The
amount of delay necessary to achieve this condition is
equal to the maximum value of the propagation delay
difference specification, PDD max, which is specified
to be 500 ns over the operating temperature range of
-40° to 100°C.
Delaying the LED signal by the maximum propaga-
tion delay difference ensures that the minimum dead
time is zero, but it does not tell a designer what the
maximum dead time will be. The maximum dead
time is equivalent to the difference between the
maximum and minimum propagation delay difference
specification as shown in Figure 27. The maximum
dead time for the HCPL-J314 is 1 µs (= 0.5 µs -
(-0.5 µs)) over the operating temperature range of
-40°C to 100°C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other
and are switching identical IGBTs.