ACPL-312U-000E Avago Technologies US Inc., ACPL-312U-000E Datasheet - Page 16

• Manufacturer Part Number: ACPL-312U-000E
• Description: OPTOCOUPLER IGBT 2.5A 8-DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of ACPL-312U-000E

• No. Of Channels: 1
• Optocoupler Output Type: Gate Drive
• Input Current: 16mA
• Output Voltage: 30V
• Opto Case Style: DIP
• No. Of Pins: 8
• Output Current: 500mA
• Output Voltage Max: 27V
• Isolation Voltage: 3.75kV
• Forward Current If: 20mA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 34. Under voltage lock out.
Under Voltage Lockout Feature.
The ACPL-312U contains an under voltage lockout (UVLO)
feature that is designed to protect the IGBT under fault
conditions which cause the ACPL-312U supply voltage
(equivalent to the fully-charged IGBT gate voltage) to
drop below a level necessary to keep the IGBT in a low re-
sistance state. When the ACPL-312U output is in the high
state and the supply voltage drops below the ACPL-312U
V
output will go into the low state with a typical delay, UVLO
Turn Off Delay, of 0.6 Ps. When the ACPL-312U output is
in the low state and the supply voltage rises above the
ACPL-312U V
optocoupler output will go into the high state (assumes
LED is “ON”) with a typical delay, UVLO Turn On Delay of
0.8 Ps.
16
Figure 35. Minimum LED skew for zero dead time.
V
V
I
I
OUT
OUT
UVLO
LED1
LED2
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
14
12
10
1
2
8
6
4
2
0
– threshold (9.5 < V
0
UVLO+
(V
CC
PDD* MAX = (t
5
- V
t
threshold (11.0 < V
PHL MAX
Q2 OFF
EE
Q1 ON
(10.7, 0.1)
(10.7, 9.2)
) – SUPPLY VOLTAGE – V
UVLO
t
PLH MIN
PHL
10
- t
– < 12.0) the optocoupler
PLH
) MAX = t
(12.3, 0.1)
(12.3, 10.8)
Q1 OFF
Q2 ON
UVLO+
PHL MAX
15
< 13.5) the
- t
PLH MIN
20
Dead Time and Propagation Delay Specifications
The ACPL-312U includes a Propagation Delay Difference
(PDD) specification intended to help designers minimize
“dead time” in their power inverter designs. Dead time
is the time period during which both the high and low
side power transistors (Q1 and Q2 in Figure 25) are off.
Any overlap in Q1 and Q2 conduction will result in large
currents flowing through the power devices between the
high and low voltage motor rails.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn off of LED1)
so that under worst-case conditions, transistor Q1 has just
turned off when transistor Q2 turns on, as shown in Figure
35. The amount of delay necessary to achieve this condition
is equal to the maximum value of the propagation delay
difference specification, PDD
350 ns over the operating temperature range of -40°C to
125°C. Delaying the LED signal by the maximum propaga-
tion delay difference ensures that the minimum dead time
is zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time is equivalent
to the difference between the maximum and minimum
propagation delay difference specifications as shown in
Figure 36. The maximum dead time for the ACPL-312U is
700 ns (= 350 ns - (-350 ns)) over an operating tempera-
ture range of -40°C to 125°C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other and
are switching identical IGBTs.
Figure 36. Waveforms for dead time.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
V
I
I
OUT 1
OUT 2
LED1
LED2
(t
PHL
PDD* MAX
Q2 OFF
Q1 ON
t
t
PHL MIN
PHL MAX
- t
PLH
) MAX
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (t
= (t
= PDD* MAX – PDD* MIN
PHL MAX
PHL MAX
t
MIN
PLH
t
MAX
PLH MAX
- t
- t
, which is specified to be
PLH MIN
PHL MIN
) + (t
) – (t
Q1 OFF
Q2 ON
PHL MIN
PLH MAX
- t
- t
PLH MAX
PLH MIN
)
)