CY3724 Cypress Semiconductor Corp, CY3724 Datasheet - Page 3

• Manufacturer Part Number: CY3724
• Description: SOCKET ADAPTER FOR CY25701
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY3724

• Accessory Type: Socket Adapter
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: CY3672, CY25701FJXC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 2. Programming Data Requirement
Table 3. Spread Percent Selection
Absolute Maximum Ratings
Supply Voltage (VDD).....................................–0.5V to +7.0V
DC Input Voltage ................................... –0.5V to V
Storage Temperature (Non-condensing) .... –55°C to +100°C
Operating Conditions
DC Electrical Characteristics
Document Number: 001-07313 Rev. *E
Notes
Down Spread
V
T
T
C
F
F
T
I
I
V
V
I
I
I
C
I
f/f
1. ±0.0% or Code “Z” for XO (No-Spread) option.
2. Guaranteed by characterization, not fully tested.
OH
OL
IH
IL
OZ
VDD
Parameter
Parameter
A
A
SSCLK
MOD
PU
DD
IH
IL
LOAD
IN
Spread
[2]
Center
Program Value
Pin Function
Pin Name
Units
Pin#
Supply voltage
Ambient temperature (commercial)
Ambient temperature (industrial)
Max. load capacitance at pin 3
SSCLK output frequency, C
Spread Spectrum Modulation Frequency
Power up time for VDD to reach minimum specified voltage (power ramp must
be monotonic)
Output high current (pin 3)
Output low current (pin 3)
Input high voltage (pin 1)
Input low voltage (pin 1)
Input high current (pin 1)
Input low current (pin 1)
Output leakage current (pin 3)
Input capacitance (pin 1)
Supply current
Initial accuracy at room temp.
Freq. stability over temp. range
Freq. stability over voltage range 3.0 to 3.6V
Aging
Percentage
Percentage
Code
Code
Description
±0.25%
–0.5%
Output Frequency
G
A
ENTER DATA
SSCLK
MHz
LOAD
3
Description
= 15 pF
±0.5%
–1.0%
V
V
CMOS levels, 70% of V
CMOS levels, 30% of V
V
V
Three-state output, OE = 0
Pin 1, or OE
V
C
T
T
T
B
H
A
A
A
OH
OL
in
in
DD
LOAD
DD
= 25°C, 3.3V
= –20°C to 70°C, 3.3V
= 25°C, First year
= V
= V
= 0.5, V
= 3.3V, SSCLK = 10 to 166 MHz,
= V
+ 0.5V
DD
SS
= 0, OE = V
DD
– 0.5, V
DD
Spread Percent Code
±0.75%
–1.5%
= 3.3V (sink)
Condition
C
J
ENTER DATA
DD
Junction Temperature ................................ –40°C to +125°C
Data Retention at Tj = 125C .................................>10 years
Package Power Dissipation...................................... 350 mW
DD
SSCLK
= 3.3V (source)
DD
DD
%
3
±1.0%
–2.0%
D
K
[1]
±1.5%
–3.0%
0.7V
3.00
30.0
0.05
Min
–20
–40
10
Min
–10
–25
–25
–12
E
L
–
10
10
–5
–
–
–
–
–
Frequency Modulation
DD
ENTER DATA 31.5
3.30
31.5
Typ
Typ
–
–
–
–
–
12
12
–
–
–
–
–
5
–
–
–
–
–
SSCLK
±2.0%
–4.0%
kHz
M
F
3
0.3V
Max
3.60
33.0
166
500
Max
70
85
15
V
10
10
10
50
25
25
12
–
–
7
5
DD
CY25701
DD
Page 3 of 9
±0.0%
±0.0%
Unit
MHz
kHz
Unit
ppm
ppm
ppm
ppm
ms
°C
°C
pF
mA
mA
mA
Z
Z
V
A
A
A
pF
V
V
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