SCFLXRAYADPTS12 Freescale Semiconductor, SCFLXRAYADPTS12 Datasheet - Page 5

• Manufacturer Part Number: SCFLXRAYADPTS12
• Description: ADAPTER BOARD FRDC
• Manufacturer: Freescale Semiconductor

Specifications of SCFLXRAYADPTS12

• Accessory Type: *
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The CD-ROM decoder performs following functions in hardware:
The CD-ROM encoder performs following functions in hardware:
1.2.13
Two full-duplex UARTs with independent receive and transmit buffers are in this module. Data formats
can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. Four-byte
receive buffers and two-byte transmit buffers minimize CPU service calls. The Dual UART module also
provides several error-detection and maskable-interrupt capabilities. Modem support includes
request-to-send (RTS) and clear-to-send (CTS) lines.
The system clock provides the clocking function from a programmable prescaler. You can select full
duplex, auto-echo loopback, local loopback, and remote loopback modes. The programmable Dual UARTs
can interrupt the CPU on various normal or error-condition events.
1.2.14
The QSPI module provides a serial peripheral interface with queued transfer capability. It supports up to
16 stacked transfers at a time, making CPU intervention between transfers unnecessary. Transfers of up to
15 Mbits/second are possible at a CPU clock of 120 MHz. The QSPI supports master mode operation only.
1.2.15
The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer.
Timer0 has an external pin TOUT0, which can be used in Output Compare mode. This mode triggers an
external signal or interrupts the CPU when the timer reaches a set value, and can also generate waveforms
on TOUT0.
The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is
derived from the system clock. In addition to the ÷1 and ÷16 clock derived from the bus clock (CPU clock
/ 2), the programmable timer-output pins either generate an active-low pulse or toggle the outputs.
Freescale Semiconductor
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Sector sync recognition
Descrambling of sectors
Verification of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors
Third-layer error correction is not performed
Sector sync recognition
Scrambling of sectors
Insertion of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors.
Third-layer error encoding needs to be done in software. This can use approximately 5–10 MHz of
performance for single-speed.
Dual UART Module
Queued Serial Peripheral Interface QSPI
Timer Module
SCF5250 Data Sheet:
Technical
Data,
Rev. 1.3
5