SCFLXRAYADPTS12 Freescale Semiconductor, SCFLXRAYADPTS12 Datasheet - Page 9

• Manufacturer Part Number: SCFLXRAYADPTS12
• Description: ADAPTER BOARD FRDC
• Manufacturer: Freescale Semiconductor

Specifications of SCFLXRAYADPTS12

• Accessory Type: *
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Address
Read-write control
Output enable
Data
Synchronous row address
strobe
Synchronous column
address strobe
SDRAM write enable
SDRAM upper byte
enable
SDRAM lower byte enable SDLDQM/GPO52
SDRAM chip selects
SDRAM clock enable
System clock
ISA bus read strobe
ISA bus write strobe
ISA bus wait signal
Chip Selects[2:0]
Buffer enable 1
Buffer enable 2
Transfer acknowledge
Wake Up
Serial Clock Line
Serial Data Line
Receive Data
Freescale Semiconductor
Signal Name
A[24:1]
A[23]/GPO54
R/W
OE
D[31:16]
SDRAS/GPIO59
SDCAS/GPIO39
SDWE/GPIO38
SDUDQM/GPO53
SD_CS0/GPIO60
BCLKE/GPIO63
BCLK/GPIO40
IDE-DIOR/GPIO31
(CS2)
IDE-DIOW/GPIO32
(CS2)
IDE-IORDY/GPIO33
CS0/CS4
CS1/QSPI_CS3/GPIO28
BUFENB1/GPIO29
BUFENB2/GPIO30
TA/GPIO12
WAKE_UP/GPIO21
SCL0/SDATA1_BS1/GPIO41
SCL1/TXD1/GPIO10
SDA0/SDATA3/GPIO42
SDA1/RXD1/GPIO44
SDA1/RXD1/GPIO44
RXD0/GPIO46
SCF5250 Data Sheet:
Mnemonic
Table 2. SCF5250 Signal Index
Technical
24 address lines, address line 23
multiplexed with GPO54 and address 24
is multiplexed with A20 (SDRAM access
only).
Bus write enable - indicates if read or
write cycle in progress
Output enable for asynchronous
memories connected to chip selects
Data bus used to transfer word data
Row address strobe for external SDRAM.
Column address strobe for external
SDRAM
Write enable for external SDRAM
Indicates during write cycle if high byte is
written
Indicates during write cycle if low byte is
written
SDRAM chip select
SDRAM clock enable
SDRAM clock output
There is 1 ISA bus read strobe and 1 ISA
bus write strobe. They allow connection
of one independent ISA bus peripherals,
e.g. an IDE slave device.
ISA bus wait line - available for both
busses
Enables peripherals at programmed
addresses.
CS[0] provides boot ROM selection
Two programmable buffer enables allow
seamless steering of external buffers to
split data and address bus in sections.
Transfer Acknowledge signal
Wake-up signal input
Clock signal for Dual I
operation
Serial data port for second I
operation
Signal is receive serial data input for
DUART
Data,
Rev. 1.3
Function
2
C module
2
C module
Output
Input/
In/Out
In/Out negated
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
In
In
negated
negated
negated
negated
negated
Reset
State
Hi-Z
X
H
–
–
–
–
–
–
–
–
–
–
–
–
–
–
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