HW-FMC-XM101-G Xilinx Inc, HW-FMC-XM101-G Datasheet - Page 21

• Manufacturer Part Number: HW-FMC-XM101-G
• Description: HARDWARE FMC INTERFACE CARD
• Manufacturer: Xilinx Inc

Specifications of HW-FMC-XM101-G

• Accessory Type: Interface Card
• For Use With/related Products: Spartan 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FMC XM101 User Guide
UG538 (v1.1) September 24, 2010
5. SMA Clock Connections
6. M24C02 2 Kb IIC EEPROM
Four SMA connectors (J2 - J5) are provided on the XM101 board.
The SMA to J1 FMC HPC connections are shown in
Table 1-13: SMA to FMC HPC Connections
An STMicroelectronics M24C02 2 Kb serial IIC bus EEPROM (U3) component provides a
small amount of non-volatile memory storage on the XM101. The IIC interface is connected
directly to the board's IIC interface as shown in
The IIC address of this component is controlled by a combination of the board's interface
and chip enable connections to the component inputs on the XM101. Signals GA0 and GA1
from the board are connected to the chip enable inputs of the M24C02 component enables
E0 and E1. Xilinx boards provide GA0 and GA1 signal strapping to 3.3V and GND signals
creating different E0 and E1 chip enable decodes on the E1 and E0 inputs of the EEPROM.
The IIC memory addressing protocol requires a bus master to initiate communication to a
peripheral device using a start condition followed by a device select code. The device select
code consists of a 4 bit Device Type Identifier and a 3-bit Chip Enable Address (E2, E1 and
E0). Bit 0 is used to indicate read/write. The Device Type Identifier for the EEPROM is 1010
binary.
Device Code Select addresses of the EEPROM when the XM101 is connected to a Xilinx
board defined in
Table 1-14: EEPROM IIC Device Select Code
The M24C02 component data sheet is available online at www.st.com.
Type Identifier
Bit 7:4 Device
CLK1_M2C_N
CLK3_M2C_N
CLK1_M2C_P
CLK3_M2C_P
Net Name
1010
Table 1-14
SMA
Bit 3
Table 1-1, page
defines the generic EEPROM Device Select Code as well as specific
0
Pin Number
Bit 2
GA0
J2.1
J3.1
J4.1
J5.1
www.xilinx.com
Bit 1
GA1
7.
Pin Number
Connector
Read/Write
Bit 0 LSB
J1 FMC
G2
G3
J2
J3
Figure 1-2, page
XM101 Board Technical Description
Table
Connected to mezzanine FMC HPC
interface
1-13.
10.
Description
21