EVL6563S-250W STMicroelectronics, EVL6563S-250W Datasheet - Page 25

• Manufacturer Part Number: EVL6563S-250W
• Description: EVAL BOARD FOR L6563(250W)
• Manufacturer: STMicroelectronics
• Type: Power Factor Correctionr

Specifications of EVL6563S-250W

• Main Purpose: Power Management, Power Factor Correction
• Embedded: No
• Utilized Ic / Part: L6563
• Primary Attributes: 250W Power Factor Correction and Preregulator Combination
• Secondary Attributes: Transition Mode & Active Tracking Boost Function.
• Board Size: 88 mm x 116 mm
• Maximum Operating Temperature: + 50 C
• Operating Supply Voltage: 90 V to 265 V
• Product: Power Management Modules
• Dimensions: 88 mm x 116 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: L6563S
• Other names: 497-10489

AN3119
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Layout hints
The layout of any converter is a very important phase in the design process needing as
much attention by the design engineers as any other design phase. Even if it the layout
phase can sometimes look time consuming a good layout surely saves time during the
functional debugging and the qualification phases. Additionally, a power supply circuit with a
correct layout needs smaller EMI filters or less filter stages and so it allows a consistent
money saving.
Converters using the L6563S do not need any special or specific layout rule to be followed;
just the general layout rules for any power converter have to be applied carefully. Basic rules
are listed below; they can be used for other PFC circuits having any power level, working
either in transition mode or with a fixed-off time control.
1.
2.
3.
4.
5.
6.
7.
Figure 37. EVL6563S-250W TM PFC: PCB layout (SMT side view)
Keep power and signal RTN separated. Connect the return pins of the components
carrying high current such as input filters, sense resistors, or output capacitors, as
close as possible. This point is the RTN star point. A downstream converter must be
connected to this return point.
Minimize the length of the traces relevant to the boost inductor, MOSFET drain, boost
rectifier and output capacitor.
Keep signal components as close as possible to each L6563S relevant pin. To be more
precise, keep the tracks relevant to the pin #1 (INV) net as short as possible.
Components and traces relevant to the Error Amplifier have to be placed far from traces
and connections carrying signals with high dV/dt, such as the MOSFET drain. For high
power converters or very compact PCB layout a 10 nF capacitor connected to pin #9
(PWM_LATCH) and pin #12 (GND) might be required to decrease the noise picked up
by this pin while it is in its high impedance status.
Please connect heat sinks to power GND.
Add an external shield to the boost inductor and connect it to power GND.
Please connect the RTN of signal components including the feedback, PFC_OK, and
MULT dividers close to the L6563S pin #12 (GND).
Connect a ceramic capacitor (100÷470 nF) to pin #14 (Vcc) and pin #12 (GND), close
to the L6563S. Connect this point to the RTN star point (see rule 1).
Doc ID 16849 Rev 2
Layout hints
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