NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 138

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

Background Debug Mode (BDM)
The assertion of BKPT should be considered in the following two special cases:
CSR[27–24] indicates the halt source, showing the highest priority source for multiple halt
conditions.
5.5.2 BDM Serial Interface
When the CPU is halted and PST reflects the halt status, the development system can send
unrestricted commands to the debug module. The debug module implements a synchronous
protocol using two inputs (DSCLK and DSI) and one output (DSO), where DSO is
specified as a delay relative to the rising edge of the processor clock. See Table 5-1. The
development system serves as the serial communication channel master and must generate
DSCLK.
The serial channel operates at a frequency from DC to 1/5 of the PSTCLK frequency. The
channel uses full-duplex mode, where data is sent and received simultaneously by both
master and slave devices. The transmission consists of 17-bit packets composed of a
status/control bit and a 16-bit data word. As shown in Figure , all state transitions are
enabled on a rising edge of the PSTCLK clock when DSCLK is high; that is, DSI is
sampled and DSO is driven.
5-16
4. The assertion of the BKPT input is treated as a pseudo-interrupt; that is, the halt
• After the system reset signal is negated, the processor waits for 16 processor clock
• The ColdFire architecture also handles a special case of BKPT being asserted while
condition is postponed until the processor core samples for halts/interrupts. The
processor samples for these conditions once during the execution of each
instruction. If there is a pending halt condition at the sample time, the processor
suspends execution and enters the halted state.
cycles before beginning reset exception processing. If the BKPT input is asserted
within eight cycles after RSTI is negated, the processor enters the halt state,
signaling halt status (0xF) on the PST outputs. While the processor is in this state,
all resources accessible through the debug module can be referenced. This is the
only chance to force the processor into emulation mode through CSR[EMU].
After system initialization, the processor’s response to the
the set of BDM commands performed while it is halted for a breakpoint.
Specifically, if the PC register was loaded, the
exit halted state and pass control to the instruction address in the PC, bypassing
normal reset exception processing. If the PC was not loaded, the
causes the processor to exit halted state and continue reset exception processing.
the processor is stopped by execution of the STOP instruction. For this case, the
processor exits the stopped mode and enters the halted state, at which point, all BDM
commands may be exercised. When restarted, the processor continues by executing
the next sequential instruction, that is, the instruction following the STOP opcode.
MCF5272 User’s Manual
GO
command causes the processor to
GO
command depends on
GO
command
MOTOROLA