NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 207

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

MOTOROLA
9.9 Solving Timing Issues with SDCR[INV]
When some SDRAM devices (such as 4 x 8 bit wide SDRAMs) are used, the SDCLK and
other control signals are more loaded than data signals. In normal MCF5272 operation, the
write data and all other control signals change with the positive edge of SDCLK. Large
capacitive loads on SDCLK can cause long delays on SDCLK, possibly causing SDRAM
hold-time violations during writes. The clock may arrive at the same time as the write data.
The write data setup time to SDCLK edge may not meet device requirements at the
SDRAM. This timing issue cannot be solved by reducing the SDCLK frequency. SDCLK
must be delayed further to meet setup/hold margin on the SDRAM data input. Setting INV
provides a 180° phase shift and moves the positive clock edge far beyond the data edge.
As Figure 9-6 shows timing relationships between SDCLK and the remaining data and
control signals can be refined by setting SDCR[INV], which inverts the SDRAM clock.
SDCR[REG] must always be cleared when SDCR[INV] is set.
.
Figure 9-5. Example Setup Time Violation on SDRAM Data Input during Write
Internal CLK
Internal CLK
Data bus
SDCLK
Data bus
SDCLK
If the delay difference between the fastest data signal and the
slowest control signal exceeds half of the clock cycle time, the
clock shift can cause hold-time violations on control signals.
Figure 9-6. Timing Refinement with Inverted SDCLK
Chapter 9. SDRAM Controller
Data setup delay
External delay of SDCLK
Data setup delay
NOTE:
Shifted delay of SDCLK
Solving Timing Issues with SDCR[INV]
9-13