NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 477

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

MOTOROLA
20.12.1 Master Reset
To perform a master reset, an external device asserts RSTI and DRESETEN simultaneously
for a minimum of six CLKIN cycles after VDD is within tolerance. This should always be
done when power is initially applied. A master reset resets the entire device including the
SDRAM controller.
Figure 20-21 is a functional timing diagram of the master reset operation, illustrating
relationships among VDD, RSTI, DRESETEN, RSTO, mode selects, and bus signals.
CLKIN must be stable by the time VDD reaches the minimum operating specification.
RSTI and DRESETEN are internally synchronized on consecutive rising and falling clocks
before being used. They must meet the specified setup and hold times to the falling edge of
CLKIN only if recognition by a specific falling edge is required
When the assertion of RSTI is recognized internally, the MCF5272 asserts the reset out pin
(RSTO). The RSTO pin is asserted as long as RSTI is asserted and remains asserted for
32,768 CLKIN cycles after RSTI is negated.
During the master reset period, all outputs are driven to their default levels. Once RSTO
negates, all bus signals continue to remain in this state until the ColdFire core begins the
first bus cycle for reset exception processing.
.
CLKIN
VDD
RSTI
DRESETEN
Mode Select
Inputs
RSTO
BUS SIGNALS
Master reset must be asserted for all power-on resets. This is
done by driving RSTI and DRESETEN low simultaneously.
Failure to assert master reset during power-on sequences
results in unpredictable DRAM controller behavior.
Figure 20-21. Master Reset Timing
Chapter 20. Bus Operation
NOTE:
CLK CYCLES
T >= 6
CLK CYCLES
T = 32,768
CLK CYCLES
T >= 22
Reset Operation
20-23