CDB4265 Cirrus Logic Inc, CDB4265 Datasheet - Page 53

• Manufacturer Part Number: CDB4265
• Description: BOARD EVAL FOR CS4265 CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4265

• Main Purpose: Audio, CODEC
• Embedded: No
• Utilized Ic / Part: CS4265
• Primary Attributes: Stereo, 24-Bit, 192 kHz Sample Rate
• Secondary Attributes: Graphic User Interface, S/PDIF/ I2S / I2C / SPI Interface
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS4265
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1001

DS657F2
11.1.1 Accessing the E Buffer
11.2
11.3
Serial Copy Management System (SCMS)
The CS4265 allows read/modify/write access to all the channel status bits. For consumer mode SCMS com-
pliance, the host microcontroller needs to manipulate the Category Code, Copy bit and L bit appropriately.
Channel Status Data E Buffer Access
The E buffer is organized as 24 x 16-bit words. For each word, the most significant byte is the A channel
data, and the least significant byte is the B channel data (see
There are two methods of accessing this memory, known as One-Byte Mode and Two-Byte Mode. The de-
sired mode is selected through a control register bit.
The user can monitor the data being transferred by reading the E buffer, which is mapped into the register
space of the CS4265, through the control port. The user can modify the data to be transmitted by writing
to the E buffer.
The E buffer is only accessible when an MCLK signal is applied to the CS4265 and the device is out of
the power-down state (the PDN bit in register 02h is cleared). If either of these conditions is not met, the
values stored in the E buffer will not change when written via the control port.
The user can configure the status register such that EFTC bit is set whenever an E to F transfer com-
pletes. With this configuration in place, periodic polling of the status register allows determination of the
time periods acceptable for E buffer interaction.
Also provided is an “E to F” inhibit bit. The “E to F” buffer transfer is disabled whenever the user sets this
bit. This may be used whenever “long” control port interactions are occurring.
A flowchart for reading and writing to the E buffer is shown in
after an E to F transfer, which is based on the output timebase.
Figure 45. Flowchart for Writing the E Buffer
Configure the EFTC status bit as
Optionally set E to F inhibit
Read the Status Register
If set, clear E to F inhibit
Is the EFTC bit set?
Rising Edge active.
Write E data
(Reg 0Dh)
Begin
Yes
No
Figure
Figure
44).
45. For writing, the sequence starts
CS4265
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