ISL6118EVAL1 Intersil, ISL6118EVAL1 Datasheet - Page 12

• Manufacturer Part Number: ISL6118EVAL1
• Description: EVALUATION PLATFORM FOR ISL6118
• Manufacturer: Intersil

Specifications of ISL6118EVAL1

• Main Purpose: Power Management, Hot Swap Controller
• Utilized Ic / Part: ISL6118
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

HIP1012A (+5V and 12V) Figures
ISL6173 (+3.3V and +2.5V)
Figure 38 shows the ISL6173 dual low voltage Hot Swap
controller. This IC targets applications between +2.1V and
+3.6V for +Vin1, with a second channel controlling
applications from +0.7V to +Vin1. The ISL6173 is biased via
+Vin1. For the following measurements, channel 1 will
control +3.3V, and channel 2 +2.5V.
Both Figures 41 and 42 show the device turning on due to
the enable lines being asserted (forced low). Figure 41
shows each output in a soft-start ramp up after being
enabled, while Figure 42 shows more detail regarding only
channel 1 (+3.3V in this case) during soft-start.
Figures 43 and 44 show an OC condition occurring during
operation on channel 1 (+3.3V). The device enters CR
mode until CT1 times out, at which point the switch on
channel 1 latches off. In Figure 44, note that (PG1)’ is
triggered upon VO1 dipping, while (FLT1)’ stays high until
CT1 times out. The nominal time-out for this device is
(CTIM*1.178)/10µA.
12
FIGURE 37. +5V AND +12V EVAL BOARD PICTURE
(Continued)
Technical Brief 457
Both Figures 45 and 46 show an OC condition occurring
during operation on channel 1 (+3.3V). Figure 45 shows the
gate signal and output voltage of channel 2 staying high
while channel 1 shuts down. Figure 46 shows the Power
Good and Fault signals for each channel, again note that
(PG1)’ and (FLT1)’ are tripped, while (PG2)’ and (FLT2)’
remain unaffected.
Figures 47 and 48 show an OC condition occurring during
operation on channel 1 (+3.3V). The device enters CR
mode but the load recovers before CT1 has a chance to time
out. Notice that (PG1)’ is triggered with the dip in VO1, then
recovers, while (FLT1)’ stays high due to CT1 never timing
out. The nominal time-out for this device is
(CTIM*1.178)/10µA.
In Figure 49, the ISL6173 is in reset mode, which means the
device will attempt to bring up channel 1 again after
discharging CT1 64 times. This process will repeat infinitely.
In the case of high di/dt shorts, a WOC condition exists (see
Figure 65). The controller will immediately pull GT to GND
before attempting to enter CR mode. Note that the load is
released before timeout occurs here.
Both channels are disabled by bringing their respective
enable lines high (see Figure 66).
April 18, 2006
TB457.0