ISL6118EVAL1 Intersil, ISL6118EVAL1 Datasheet - Page 8

• Manufacturer Part Number: ISL6118EVAL1
• Description: EVALUATION PLATFORM FOR ISL6118
• Manufacturer: Intersil

Specifications of ISL6118EVAL1

• Main Purpose: Power Management, Hot Swap Controller
• Utilized Ic / Part: ISL6118
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

HIP1012A (+5V and +3.3V)
Figures 23 and 24 show the HIP1012A dual Hot Swap
controller. To configure for +3.3V and +5V, remove JP1, and
apply a function generator at pin2 of JP1 for (PWRON2)’.
Figures 25 and 26 show the HIP1012A dual Hot Swap
controller load card.
Both Figures 27 and 28 show the same event. Figure 27
shows 5VG and Figure 28 shows I
asserted (forced low), notice the soft-start ramp of 3/12VG to
assure inrush current is limited. Observe the PGOOD delay
as well.
HIP1012A (+5V and +3.3V) Figures
TABLE 1. HOT SWAP CONTROLLER LOAD CARD
3 /12VIN
Note: Test point number equals HIP1012A pin number.
10 = 1.8Ω (1.8A)
01 = 1.0Ω (3.3A)
11 = 0.7Ω (4.7A)
GND
GND
3.3V LOAD
5V
00 = Off
IN
V
CEC1
DD
1
0.1µF
Q
1
8
C
3.3V
20Ω
5
R
JP1
3
. After PWRON2 is
01 = 10.1Ω (0.5A)
10 = 7.0Ω (0.7A)
11 = 4.2Ω (1.2A)
JP2
FIGURE 23. HIP1012A EVAL BOARD SCHEMATIC
5V LOAD
00 = Off
C
0.01µF
Q
3
2
Technical Brief 457
JP4
1
2
3
4
5
6
7
20Ω
R
R
3/12VS
3/12VG
V
MODE/
PWRON1
PWRON2
5VG
5VS
4
101
DD
U1
20mΩ
100mΩ
0.1µF
JP3
C
R
R
2
1
LED1
1
3/12ISEN
Figures 29 and 30 both show the same event. Figure 29
shows 5VG and Figure 30 shows I
shutdown by forcing PWRON2 high.
Figures 31 and 32 show turning on into an OC condition.
Figure 31 shows 3/12VG and PWRON2, while Figure 32
shows I
current through the sense resistor exceeds the user
programmed OC threshold (see data sheet). The controller
enters CR mode and capacitor CTIM begins charging. The
nominal time-out period is CTIM x 200kΩ.
Both Figures 33 and 34 show an OC event. Figure 33 shows
a 700mA to 1.2A load step into OC range during normal
operation, while Figure 34 shows a short occurring during
normal operation. Notice that in the “short condition”, Figure
34, 5VG is pulled instantly to GND, then slowly ramped up.
An OC event occurs on the 5V line. Notice that the 3.3V line
continues operating normally until CTIM times out and the
device latches off (see Figure 35).
PGOOD
CPUMP
5VISEN
RILIM
CTIM
GND
0.01µF
C
4
5V
14
13
12
11
10
9
8
and PGOOD. An OC event occurs when the
10kΩ
R
5
C
0.047µF
2
3.3V
. Controller is
CEC2
3 / 12VOUT
GND
GND
5VOUT
April 18, 2006
TB457.0