DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 246
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DS26528DK
Manufacturer Part Number
DS26528DK
Description
KIT DESIGN FOR DS26528
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26528G.pdf
(276 pages)
Specifications of DS26528DK
Main Purpose
Telecom, Framer and Line Interface Units (LIUs)
Utilized Ic / Part
G575DS26528
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Figure 10-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)
Figure 10-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
RCHBLK
RSYSCLK
RCHBLK
RSYSCLK
RMSYNC
RCHCLK
RMSYNC
RCHCLK
RSYNC
NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS
MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO ONE).
NOTE 2: RSYNC IN THE OUTPUT MODE (RIOCR.2 = 0).
NOTE 3: RSYNC IN THE INPUT MODE (RIOCR.2 = 1).
NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
RSYNC
RSYNC
RSYNC
RSER
NOTE 1: RSYNC IN THE OUTPUT MODE (RIOCR.2 = 0).
NOTE 2: RSYNC IN THE INPUT MODE (RIOCR.2 = 1).
NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
NOTE 4: RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1.
RSER
RSIG
2
1
3
3
1
2
4
CHANNEL 23/31
CHANNEL 31
A
CHANNEL 31
B
LSB
C
MSB
LSB MSB
D
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CHANNEL 24/32
CHANNEL 32
A
CHANNEL 32
B
LSB
C
LSB MSB
DS26528 Octal T1/E1/J1 Transceiver
F
D
MSB
CHANNEL 1
CHANNEL 1/2
CHANNEL 1
Note 4
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