EVAL-AD7797EBZ Analog Devices Inc, EVAL-AD7797EBZ Datasheet - Page 4

• Manufacturer Part Number: EVAL-AD7797EBZ
• Description: BOARD EVALUATION FOR AD7797
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7797EBZ

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 123
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF/128
• Power (typ) @ Conditions: 1.6mW @ 123SPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7797
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7796/AD7797
Parameter
INTERNAL/EXTERNAL CLOCK
LOGIC INPUTS
SCLK, CLK, and
LOGIC OUTPUTS (INCLUDING CLK)
SYSTEM CALIBRATION
POWER REQUIREMENTS
1
2
3
4
5
6
7
Temperature range is –40°C to +85°C.
Specification is not production tested, but is supported by characterization data at initial product release.
Following a calibration, this error is in the order of the noise for the update rate selected.
Recalibration at any temperature removes these errors.
Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AV
FS[3:0] are the four bits used in the mode register to select the output word rate.
Digital inputs equal to DV
Internal Clock
External Clock
CS
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current
Floating-State Output Capacitance
Data Output Coding
Full-Scale Calibration Limit
Zero-Scale Calibration Limit
Input Span
Power Supply Voltage
Power Supply Currents
DIN (Schmitt-Triggered Input)
V
V
V
V
V
V
Input Currents
Input Capacitance
T
T
T
T
T
T
(+)
(–)
(+) − V
(+)
(–)
(+) − V
Frequency
Duty Cycle
Frequency
Duty Cycle
2
Input Low Voltage, V
AV
DV
I
I
Input High Voltage, V
DD
DD
DD
DD
Current
(Power-Down Mode)
– GND
– GND
T
T
(–)
(–)
2
2
DD
7
or GND.
OL
INL
OH
INH
2
2
2
AD7796B/AD7797B
64 ± 3%
50:50
64
45:55 to 55:45
0.8
0.4
2.0
1.4/2
0.8/1.7
0.1/0.17
0.9/2
0.4/1.35
0.06/0.13
±10
10
DV
4
0.4
0.4
±10
10
Offset Binary
+1.05 × FS
−1.05 × FS
0.8 × FS
2.1 × FS
2.7/5.25
2.7/5.25
325
1
DD
− 0.6
Rev. A | Page 4 of 24
1
Unit
kHz min/max
% typ
kHz nom
% typ
V max
V max
V min
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
μA max
pF typ
V min
V min
V max
V max
μA max
pF typ
V max
V min
V min
V max
V min/max
V min/max
μA max
μA max
Test Conditions/Comments
A 128 kHz clock can be used if the divide by 2
function is used (Bit CLK1 = CLK0 = 1)
Applies for external 64 kHz clock (a 128 kHz
clock can have a less stringent duty cycle)
DV
DV
DV
DV
DV
DV
DV
DV
DV
V
All digital inputs
DV
DV
DV
DV
250 μA typ @ AV
IN
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
= DV
= 5 V, I
= 5 V
= 3 V
= 3 V or 5 V
= 5 V
= 5 V
= 5 V
= 3 V
= 3 V
= 3 V
= 3 V, I
= 5 V, I
= 3 V, I
DD
= 4 V, T
DD
or GND
SINK
SOURCE
SOURCE
SINK
A
= 25°C).
= 1.6 mA (DOUT/RDY)/800 μA (CLK)
= 100 μA
DD
= 100 μA
= 200 μA
= 3 V, 280 μA typ @ AV
DD
= 5 V