EVAL-AD7643CBZ Analog Devices Inc, EVAL-AD7643CBZ Datasheet - Page 5

• Manufacturer Part Number: EVAL-AD7643CBZ
• Description: BOARD EVALUATION FOR AD7643
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7643CBZ

• Number Of Adc's: 1
• Number Of Bits: 18
• Sampling Rate (per Second): 1.25M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 65mW @ 1.25MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7643
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V
Table 3.
Parameter
CONVERSION AND RESET (Refer to Figure 30 and Figure 31)
PARALLEL INTERFACE MODES (Refer to Figure 32 to Figure 35 )
MASTER SERIAL INTERFACE MODES
SLAVE SERIAL INTERFACE MODES (Refer to Figure 39 and Figure 40)
1
2
3
4
See the Conversion Control section.
See the Digital Interface section and the RESET section.
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.
Convert Pulse Width
Time Between Conversions
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert)
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time
Acquisition Time
RESET Pulse Width
RESET Low to BUSY High Delay
BUSY High Time from RESET Low
CNVST Low to Data Valid Delay
Data Valid to BUSY Low Delay
Bus Access Request to Data Valid
Bus Relinquish Time
CS Low to SYNC Valid Delay
CS Low to Internal SCLK Valid Delay
CS Low to SDOUT Delay
CNVST Low to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
Internal SCLK High
Internal SCLK Low
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
CS High to SYNC Hi-Z
CS High to Internal SCLK Hi-Z
CS High to SDOUT Hi-Z
BUSY High in Master Serial Read After Convert
CNVST Low to SYNC Asserted Delay
SYNC Deasserted to BUSY Low Delay
External SCLK Set-Up Time
External SCLK Active Edge to SDOUT Delay
SDIN Set-Up Time
SDIN Hold Time
External SCLK Period
External SCLK High
External SCLK Low
4
4
4
4
4
4
2
2
3
(Refer to Figure 36 and Figure 37)
3
4
REF
= 2.5 V; all specifications T
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L
MIN
of 10 pF; otherwise, the load is 60 pF maximum.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
to T
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
38
39
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
MAX
, unless otherwise noted.
Min
15
800
10
250
15
2
2
2
8
2
2
1
0
0
5
1
5
5
12.5
5
5
Typ
1
10
500
135
See Table 4
508
13
Max
70
23
550
550
550
20
15
10
10
10
20
10
10
10
8
AD7643
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns