EVAL-AD7643CBZ Analog Devices Inc, EVAL-AD7643CBZ Datasheet - Page 6

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EVAL-AD7643CBZ

Manufacturer Part Number
EVAL-AD7643CBZ
Description
BOARD EVALUATION FOR AD7643
Manufacturer
Analog Devices Inc
Series
PulSAR®r
Datasheets

Specifications of EVAL-AD7643CBZ

Number Of Adc's
1
Number Of Bits
18
Sampling Rate (per Second)
1.25M
Data Interface
Serial, Parallel
Inputs Per Adc
1 Differential
Input Range
±VREF
Power (typ) @ Conditions
65mW @ 1.25MSPS
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD7643
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD7643
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK High Minimum
Internal SCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
BUSY High Width Maximum
TO OUTPUT
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD
C
L
Figure 2. Load Circuit for Digital Interface Timing,
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
SDOUT, SYNC, and SCLK Outputs, C
PIN
50pF
C
L
500µA
500µA
I
I
OL
OH
1.4V
L
= 10 pF
Rev. 0 | Page 6 of 28
Symbol
t
t
t
t
t
t
t
t
t
18
19
19
20
21
22
23
24
28
t
DELAY
0.8V
0
0
1
8
20
2
2
1
0
0
0.84
Figure 3. Voltage Reference Levels for Timing
0
1
3
16
40
8
8
5
0.5
0.5
1.14
2V
0.8V
1
0
3
32
70
16
16
5
10
9
1.72
2V
1
1
3
64
135
32
32
5
30
26
2.88
t
DELAY
2V
0.8V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs

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