EVAL-AD7676CBZ Analog Devices Inc, EVAL-AD7676CBZ Datasheet - Page 16

• Manufacturer Part Number: EVAL-AD7676CBZ
• Description: BOARD EVALUATION FOR AD7676
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7676CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 67mW @ 500kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In Read-after-Conversion Mode, unlike in other modes, it should
be noted that the signal BUSY returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
In Read-during-Conversion Mode, the serial clock and data
toggle at appropriate instances, which minimizes potential feed-
through between digital activity and the critical conversion decisions.
SLAVE SERIAL INTERFACE
External Clock
The AD7676 is configured to accept an externally supplied serial
data clock on the SCLK pin when the EXT/INT pin is held HIGH.
In this mode, several methods can be used to read the data. The
external serial clock is gated by CS and the data are output when
both CS and RD are LOW. Thus, depending on CS, the data can
be read after each conversion or during the following conversion.
The external clock can be either a continuous or discontinuous
clock. A discontinuous clock can be either normally HIGH or
normally LOW when inactive. Figures 19 and 20 show the detailed
timing diagrams of these methods. Usually, because the AD7676
has a longer acquisition phase than the conversion phase, the
data are read immediately after conversion.
While the AD7676 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is particu-
larly important during the second half of the conversion phase
because the AD7676 provides error correction circuitry that can
correct for an improper bit decision made during the first half of
the conversion phase. For this reason, it is recommended that when
AD7676
SDOUT
BUSY
SCLK
SDIN
CS
Figure 19. Slave Serial Data Timing for Reading (Read after Conversion)
t
t
16
31
t
33
X
t
36
1
t
35
D15
X15
t
37
t
34
2
EXT/INT = 1
X14
D14
t
32
3
X13
D13
–16–
an external clock is being provided, it is a discontinuous clock
that is toggling only when BUSY is LOW or, more importantly,
that it does not transition during the latter half of BUSY HIGH.
External Discontinuous Clock Data Read after Conversion
This mode is the most recommended of the serial slave modes.
Figure 19 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
LOW, the result of this conversion can be read while both CS and
RD are LOW. The data is shifted out, MSB first, with 16 clock
pulses and is valid on both the rising and falling edges of the clock.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients
on the digital interface during the conversion process.
Another advantage is to be able to read the data at any speed up to
40 MHz, which accommodates both slow digital host interface
and the fastest serial reading.
Finally, in this mode only, the AD7676 provides a “daisy chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing component
count and wiring connections when it is desired as it is, for
instance, in isolated multiconverter applications.
An example of the concatenation of two devices is shown in
Figure 21. Simultaneous sampling is possible by using a common
CNVST signal. It should be noted that the RDC/SDIN input is
latched on the opposite edge of SCLK of the one used to shift
out the data on SDOUT. Thus, the MSB of the “upstream”
converter just follows the LSB of the “downstream” converter
on the next SCLK cycle.
INVSCLK = 0
14
15
D1
X1
RD = 0
16
D0
X0
17
X15
Y15
18
X14
Y14
REV. B