EVAL-AD7676CBZ Analog Devices Inc, EVAL-AD7676CBZ Datasheet - Page 6

• Manufacturer Part Number: EVAL-AD7676CBZ
• Description: BOARD EVALUATION FOR AD7676
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7676CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 67mW @ 500kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7676
Pin No. Mnemonic
21
22
23
24
25–28
29
30
31
32
33
34
35
36
37
38
39
43
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
D[8]
or SDOUT
D[9]
or SCLK
D[10]
or SYNC
D[11]
or RDERROR
D[12:15]
BUSY
DGND
RD
CS
RESET
PD
CNVST
AGND
REF
REFGND
IN–
IN+
Type
DO
DI/O
DO
DO
DO
DO
P
DI
DI
DI
DI
DI
P
AI
AI
AI
AI
SER/PAR is HIGH, this output, part of the Serial Port, is used as a serial data output synchronized
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless
Must Be Tied to Digital Ground
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions
Must Be Tied to Analog Ground
Reference Input Voltage
Reference Input Analog Ground
Differential Negative Analog Input
Differential Positive Analog Input
Description
When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. When
to SCLK. Conversion results are stored in an on-chip register. The AD7676 provides the conversion
result, MSB first, from its internal shift register. The DATA format is determined by the logic level
of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK.
In Serial Mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge.
When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input or
output, depending on the logic state of the EXT/INT pin. The active edge where the data SDOUT
is updated depends on the logic state of the INVSCLK pin.
When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this output, part of the Serial Port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read
sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while
SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is
driven LOW and remains LOW while SDOUT output is valid.
When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is used as
an incomplete read error flag. In Slave Mode, when a data read is started and not complete when
the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH.
of the state of SER/PAR.
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could
be used as a data-ready clock signal.
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
CS is also used to gate the external serial clock.
Reset Input. When set to a logic HIGH, resets the AD7676. Current conversion if any is aborted.
are inhibited after the current one is completed.
Start Conversion. If CNVST is HIGH when the acquisition phase (t
edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion.
This mode is the most appropriate if low sampling jitter is desired. If CNVST is LOW when the
acquisition phase (t
conversion is started immediately.
PIN FUNCTION DESCRIPTIONS (continued)
8
) is complete, the internal sample-and-hold is put into the hold state and a
–6–
8
) is complete, the next falling
REV. B