CDB5534U Cirrus Logic Inc, CDB5534U Datasheet - Page 30

• Manufacturer Part Number: CDB5534U
• Description: EVAL BOARD FOR CS5534
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5534U

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 3.84k
• Data Interface: Serial
• Inputs Per Adc: 2 Single
• Input Range: 0 ~ 2.5 V
• Power (typ) @ Conditions: 35mW @ 5 V
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5534
• Description/function: Audio DSPs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: C8051F320
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1016

2.5. Calibration
Calibration is used to set the zero and gain slope of
the ADC’s transfer function. The CS5531/32/33/34
offer both self-calibration and system calibration.
Note:
2.5.1. Calibration Registers
The CS5531/32/33/34 converters have an individu-
al offset and gain register for each channel input.
The gain and offset registers, which are used during
both self and system calibration, are used to set the
zero and gain slope of the converter’s transfer func-
tion. As shown in Offset Register section, one LSB
in the offset register is 1.835007966 x 2
2.5.2. Gain Register
The gain register span is from 0 to (64-2
2.5.3. Offset Register
One LSB represents 1.835007966 X 2
Offset and data word bits align by MSB. After reset, all bits are ‘0’.
The offset register is stored as a 32-bit, two’s complement number, where the last 8 bits are all 0.
30
MSB
MSB
Sign
D15
D15
2
NU
2
-17
0
0
0
0
-9
D30
D14
D30
D14
2
2
NU
2
After the ADCs are reset, they are functional
and can perform measurements without
being calibrated (remember that the VRS bit
in the configuration register must be properly
configured). In this case, the converter will
utilize the initialized values of the on-chip
registers (Gain = 1.0, Offset = 0.0) to
calculate output words. Any initial offset and
gain errors in the internal circuitry of the chip
will remain.
0
-10
0
0
-18
0
-2
D29
D29
D13
D13
2
2
2
2
0
-11
0
0
-19
0
-3
5
D28
D12
D28
D12
2
2
2
2
0
-12
0
0
-20
0
-4
4
D27
D11
D27
D11
2
2
2
2
-13
-21
0
0
0
0
-5
3
D26
D10
D26
D10
2
2
2
2
-24
0
-14
0
0
-22
0
-6
2
-24
proportion of the input span (bipolar span is 2 times unipolar span).
). After Reset D24 is 1, all other bits are ‘0’.
-24
D25
D25
2
2
D9
2
D9
2
0
-15
0
0
-23
0
-7
1
propor-
D24
D24
2
2
D8
2
D8
2
1
-16
0
0
-24
0
-8
0
D23
D23
2
tion of the input span (bipolar span is 2 times the
unipolar span, gain register = 1.000...000 decimal).
The MSB in the offset register determines if the
offset to be trimmed is positive or negative (0 pos-
itive, 1 negative). Note that the magnitude of the
offset that is trimmed from the input is mapped
through the gain register. The converter can typi-
cally trim ±100% of the input span. As shown in the
Gain Register section, the gain register spans from
0 to (64 - 2
the gain register is
where the binary numbers have a value of either
zero or one (b
While gain register settings of up to 64 - 2
available, the gain register should never be set to
values above 40.
NU
2
D7
2
D7
D
-17
0
0
0
0
-1
-9
=
b
D29
D22
D22
2
2
NU
2
D6
D6
2
0
-18
0
-10
0
0
-2
5
+
b
-24
D28
D21
D21
2
2
NU
2
D5
D5
). The decimal equivalent meaning of
2
0
-19
0
-11
0
0
-3
D29
4
+
b
D27
is the binary value of bit D29).
CS5531/32/33/34-AS
D20
D20
2
2
NU
2
D4
D4
2
0
-20
0
-12
0
0
-4
3
+
…
+
D19
D19
2
2
NU
2
D3
D3
b
0
-21
0
-13
0
0
D0
-5
2
–
24
D18
D18
)
2
2
NU
2
D2
D2
-14
0
0
0
0
=
22
-6
i
∑
29
=
0
b
D17
D17
2
2
Di
NU
D1
D1
2
0
-23
0
-15
0
0
-7
2
(
DS289F5
–
24
-24
+
LSB
LSB
D16
D16
2
2
NU
2
i
0
-24
0
-16
0
0
)
-8
are