CDB53L21 Cirrus Logic Inc, CDB53L21 Datasheet - Page 15

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CDB53L21

Manufacturer Part Number
CDB53L21
Description
BOARD EVAL FOR CS53L21 ADC
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CDB53L21

Number Of Adc's
2
Number Of Bits
24
Sampling Rate (per Second)
96k
Data Interface
Serial
Inputs Per Adc
3 Single Ended
Input Range
±2.5 V
Power (typ) @ Conditions
22.45mW @ 48kSPS, 2.5 V
Voltage Supply Source
Analog and Digital
Operating Temperature
-10°C ~ 70°C
Utilized Ic / Part
CS53L21
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
598-1550
DS700PP1
Master Mode
Output Sample Rate (LRCK)
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
7. After powering up the CS53L21, RESET should be held low after the power supplies and clocks are
8. See
9.
10. “MCLK” refers to the external master clock applied.
settled.
See“Master” on page
(Note 9)
“Example System Clock Frequencies” on page 57
SDOUT
SDOUT
LRCK
LRCK
SCLK
SCLK
Parameters
Figure 4. Serial Audio Interface Master Mode Timing
Figure 3. Serial Audio Interface Slave Mode Timing
30.
t
t
t
s(LK-SK)
d(MSB)
d(MSB)
All Speed Modes
MSB
MSB
//
//
//
//
//
//
//
//
//
//
t
t
h(SK-SDO)
h(SK-SDO)
(Note 10)
t
t
P
P
for typical MCLK frequencies.
//
//
t
t
Symbol
s(SDO-SK)
h(SK-SDO)
t
d(MSB)
1/t
F
s
P
MSB-1
MSB-1
t
t
s(SDO-SK)
s(SDO-SK)
Min
45
45
20
30
-
-
-
MCLK
---------------- -
128
64•F
Max
55
55
52
-
-
CS53L21
s
Units
Hz
Hz
ns
ns
ns
%
%
15

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