CDB53L21 Cirrus Logic Inc, CDB53L21 Datasheet - Page 32

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CDB53L21

Manufacturer Part Number
CDB53L21
Description
BOARD EVAL FOR CS53L21 ADC
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CDB53L21

Number Of Adc's
2
Number Of Bits
24
Sampling Rate (per Second)
96k
Data Interface
Serial
Inputs Per Adc
3 Single Ended
Input Range
±2.5 V
Power (typ) @ Conditions
22.45mW @ 48kSPS, 2.5 V
Voltage Supply Source
Analog and Digital
Operating Temperature
-10°C ~ 70°C
Utilized Ic / Part
CS53L21
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
598-1550
32
4.7
4.8
LRCK
SCLK
SDIN
Initialization
The initialization and Power-Down sequence flowchart is shown in
Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modulators
and control port registers are reset. The internal voltage reference, ADC and switched-capacitor low-pass
filters are powered down.
The device will remain in the Power-Down state until the RESET pin is brought high. The control port is ac-
cessible once RESET is high and the desired register settings can be loaded per the interface descriptions
in
10 ms, the A/D will enter Hardware Mode.
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+ will begin powering
up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then ap-
plied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a muted
state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the
MCLK/LRCK frequency ratio and normal operation begins.
Recommended Power-Up Sequence
1. Hold RESET low until the power supplies are stable.
2. Bring RESET high. After approximately 10 ms, the device will enter Hardware Mode.
3. For Software Mode operation, set the PDN bit to ‘1’b in under 10 ms. This will place the device in “stand-
4. Load the desired register settings while keeping the PDN bit set to ‘1’b.
5. Start MCLK to the appropriate frequency, as discussed in
6. Set the PDN bit to ‘0’b.
7. Apply LRCK and SCLK for normal operation to begin.
8. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
M S B
“Software Mode” on page
by”.
prevent power glitch related issues.
AOUTA / AINxA
L eft C h a n n e l
34. If a valid write sequence to the control port is not made within approximately
Figure 16. Left-Justified Format
L S B
M S B
Section
AOUTB / AINxB
R ig ht C h a n n el
Figure 17 on page
4.5.
33. The A/D enters a
L S B
CS53L21
DS700PP1
MSB

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