HI5805EVAL1 Intersil, HI5805EVAL1 Datasheet - Page 8

• Manufacturer Part Number: HI5805EVAL1
• Description: EVALUATION PLATFORM HI5805
• Manufacturer: Intersil

Specifications of HI5805EVAL1

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 5M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 4 Vpp
• Power (typ) @ Conditions: 300mW @ 5MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: HI5805
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Descriptions
Detailed Description
Theory of Operation
The HI5805 is a 12-bit, fully-differential, sampling pipeline A/D
converter with digital error correction. Figure 14 depicts the
circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
clock which is a non-overlapping two phase signal, f
derived from the master clock. During the sampling phase, f
the input signal is applied to the sampling capacitors, C
the same time the holding capacitors, C
analog ground. At the falling edge of f
sampled on the bottom plates of the sampling capacitors. In
the next clock phase, f
sampling capacitors are connected together and the holding
capacitors are switched to the op-amp output nodes. The
charge then redistributes between C
sample-and-hold cycle. The output is a fully-differential,
sampled-data representation of the analog input. The circuit
not only performs the sample-and-hold function but will also
convert a single-ended input to a fully-differential output for
the converter core. During the sampling phase, the V
PIN NO.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
DV
D
DV
D
V
D
DV
NAME
AV
A
A
AV
V
V
V
CLK
V
ROUT
D11
D10
GND1
GND1
GND2
GND
GND
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IN
RIN
DC
IN
CC1
CC1
CC2
CC
CC
+
-
Input Clock.
Digital Supply (5.0V).
Digital Ground.
Digital Supply (5.0V).
Digital Ground
Analog Supply (5.0V).
Analog Ground.
Positive Analog Input.
Negative Analog Input.
DC Bias Voltage Output.
Reference Voltage Output.
Reference Voltage Input.
Analog Ground.
Analog Supply (5.0V).
Data Bit 11 Output (MSB).
Data Bit 10 Output.
Data Bit 9 Output.
Data Bit 8 Output.
Data Bit 7 Output.
Data Bit 6 Output.
Digital Output Ground.
Digital Output Supply (3.0V to 5.0V).
Data Bit 5 Output.
Data Bit 4 Output.
Data Bit 3 Output.
Data Bit 2 Output.
Data Bit 1 Output.
Data Bit 0 Output (LSB).
2
, the two bottom plates of the
8
DESCRIPTION
S
1
and C
the input signal is
H
, are discharged to
H
completing one
1
IN
and f
S
pins
. At
2
1
,
,
HI5805
see only the on-resistance of a switch and C
small values of these components result in a typical full power
input bandwidth of 100MHz for the converter.
As illustrated in the functional block diagram and the timing
diagram in Figure 1, three identical pipeline subconverter
stages, each containing a four-bit flash converter, a four-bit
digital-to-analog converter and an amplifier with a voltage
gain of 8, follow the S/H circuit with the fourth stage being
only a 4-bit flash converter. Each converter stage in the
pipeline will be sampling in one phase and amplifying in the
other clock phase. Each individual sub-converter clock
signal is offset by 180 degrees from the previous stage
clock signal, with the result that alternate stages in the
pipeline will perform the same operation.
The 4-bit digital output of each stage is fed to a digital delay
line controlled by the internal clock. The purpose of the delay
line is to align the digital output data to the corresponding
sampled analog input signal. This delayed data is fed to the
digital error correction circuit which corrects the error in the
output data with the information contained in the redundant
bits to form the final 12-bit output for the converter.
Because of the pipeline nature of this converter, the data on
the bus is output at the 3rd cycle of the clock after the analog
sample is taken. This delay is specified as the data latency.
After the data latency time, the data representing each
succeeding sample is output at the following clock pulse. The
output data is synchronized to the external clock by a latch.
The digital outputs are in offset binary format (See Table 1).
Internal Reference Generator, V
The HI5805 has an internal reference generator, therefore, no
external reference voltage is required. V
connected to V
The HI5805 can be used with an external reference. The
converter requires only one external reference voltage
connected to the V
The HI5805 is tested with V
converter, two reference voltages of 1.3V and 3.3V are
generated for a fully differential input signal range of ±2V.
In order to minimize overall converter noise, it is
recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, V
FIGURE 14. ANALOG INPUT SAMPLE-AND-HOLD
V
V
IN
IN
+
-
φ
φ
φ
RIN
1
1
2
when using the internal reference voltage.
RIN
C
C
S
S
φ
pin with V
1
φ
RIN
1
equal to 3.5V. Internal to the
ROUT
C
C
-
+
H
H
+
-
ROUT
ROUT
left open.
φ
1
S
φ
. The relatively
and V
RIN
must be
1
V
V
.
OUT
OUT
RIN
+
-